ETA9351Q4Y

@@ -0,0 +1,66 @@+# ETA9351Q4Y++**etasolution** · Power Management - Specialized · QFN-24L-EP(4x4)++ETA9351Q4Y from etasolution, in a QFN-24L-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PGND3 | power_in | Power ground for Channel 3 buck converter. Return path for the low-side NMOS switch current; route with a low-impedance connection to the input/output capacitor grounds. |+| 2 | EN3 | input | Enable input for Channel 3. Drive high (>1.5 V) to enable the channel, low (<0.4 V) to disable. EN input current ~1 uA. |+| 3 | NC | unconnected | No internal connection. Per the PCB Layout Guide (page 7) this pin is used as a routing island; PGND2 (pin 11) is jumpered through the exposed pad to pin 3 to shorten the Channel 2 input capacitor return path. |+| 4 | VIN2 | power_in | Input supply voltage for Channel 2 (2.6 V to 5.5 V). Bypass with a 22 uF ceramic capacitor to PGND2 and a 10 nF capacitor to AGND2. |+| 5 | SW2 | output | Switching node for Channel 2. Connect a 1 uH inductor between SW2 and VOS2. Internally driven by the high-side PMOS and low-side NMOS power switches; SW current is internally limited (~4.5 A typ). |+| 6 | EN2 | input | Enable input for Channel 2. Drive high (>1.5 V) to enable the channel, low (<0.4 V) to disable. |+| 7 | VIN1 | power_in | Input supply voltage for Channel 1 (2.6 V to 5.5 V). Bypass with a 22 uF ceramic capacitor to PGND1 and a 10 nF capacitor to AGND1. |+| 8 | EN1 | input | Enable input for Channel 1. Drive high (>1.5 V) to enable the channel, low (<0.4 V) to disable. |+| 9 | PGND1 | power_in | Power ground for Channel 1 buck converter. Return path for the low-side NMOS switch current. |+| 10 | SW1 | output | Switching node for Channel 1. Connect a 1 uH inductor between SW1 and VOS1. |+| 11 | PGND2 | power_in | Power ground for Channel 2 buck converter. Per the PCB Layout Guide, route through the bottom exposed heat-dissipation pad over to pin 3 to shorten the Channel 2 input capacitor return path. |+| 12 | FB1 | input | Feedback input for Channel 1. Connect an external resistor divider from VOUT1 to FB1 and AGND1 to program the output between 0.45 V and VIN1. Regulation threshold is 0.45 V (0.441 V / 0.459 V min/max); input current ~0.01 uA. |+| 13 | AGND1 | power_in | Analog ground for Channel 1. Keep quiet by adding a 10 nF ceramic capacitor from VIN1 to AGND1. |+| 14 | VOS1 | input | Output voltage sense input for Channel 1. Connect directly to the Channel 1 regulated output node (post-inductor) for the internal on-time / voltage-mode control loop. |+| 15 | FB2 | input | Feedback input for Channel 2. Connect an external resistor divider from VOUT2 to FB2 and AGND2 to program the output between 0.45 V and VIN2. |+| 16 | AGND2 | power_in | Analog ground for Channel 2. Add a 10 nF ceramic capacitor from VIN2 to AGND2 to keep this reference quiet. |+| 17 | VOS2 | input | Output voltage sense input for Channel 2. Connect directly to the Channel 2 regulated output node. |+| 18 | FB3 | input | Feedback input for Channel 3. Connect an external resistor divider from VOUT3 to FB3 and AGND3 to program the output between 0.45 V and VIN3. |+| 19 | AGND3 | power_in | Analog ground for Channel 3. Add a 10 nF ceramic capacitor from VIN3 to AGND3 to keep this reference quiet. |+| 20 | VOS3 | input | Output voltage sense input for Channel 3. Connect directly to the Channel 3 regulated output node. |+| 21 | PG3 | output | Power-Good open-drain output for Channel 3. High-impedance when VOUT3 is within regulation (rising threshold 90% of nominal, 2.5% hysteresis); pulls low (VOL <=0.4 V at 1 mA sink) when VOUT3 is below its nominal value. The external pull-up must not exceed VIN3. |+| 22 | SW3 | output | Switching node for Channel 3. Connect a 1 uH inductor between SW3 and VOS3. |+| 23 | PVIN3 | power_in | Power input supply for Channel 3 (2.6 V to 5.5 V). Feeds the Channel 3 high-side PMOS power switch. Bypass with a 22 uF ceramic capacitor to PGND3 and a 10 nF capacitor to AGND3; tie together with AVIN3. |+| 24 | AVIN3 | power_in | Analog input supply for Channel 3 (2.6 V to 5.5 V). Feeds the Channel 3 analog/control circuitry. Bypass with a 22 uF ceramic capacitor to PGND3 and a 10 nF capacitor to AGND3; typically tied to PVIN3. |+| 25 | GND | power_in | Exposed thermal pad on the bottom of the QFN-24 package. Must be soldered to the PCB ground plane for electrical ground and thermal dissipation (theta-JA = 30 degC/W). Also serves as a routing plane between PGND2 (pin 11) and pin 3 per the PCB Layout Guide. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | etasolution |+| Package | QFN-24L-EP(4x4) |+| Category | Power Management (PMIC) |+| Pins | 25 |++## Ordering variants++Same part, different packaging or reel option.++- `ETA9351Q4Y`++## CAD (KiCad official)++- Symbol: `ETA9351Q4Y`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm`+- 3D model: QFN-24L-EP(4x4) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [etasolution datasheet](docs/eta9351q4y-datasheet.pdf) (9 pp, sha256 `b31a7ee0be5fc574`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/eta9351q4y-datasheet.pdf)

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