component
ESP32-S3R16V
Public Made by Adomby adom
Espressif Systems RF and Wireless, 56-VFQFN Exposed Pad. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Publish 0.1.0
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README.md+146docs/esp32-s3r16v-datasheet.pdfdocs/hero.pngesp32-s3r16v-etched.glbesp32-s3r16v-hero.glbesp32-s3r16v-hero.overlay.json+1329esp32-s3r16v.glbesp32-s3r16v.kicad_mod+781esp32-s3r16v.kicad_sym+1124esp32-s3r16v.lbr+280esp32-s3r16v.step+14216package.json+487page.json+493viewers/footprint.html+1viewers/symbol.html+1README.mdadded+146@@ -0,0 +1,146 @@+# ESP32-S3R16V++**Espressif Systems** · RF and Wireless · 56-VFQFN Exposed Pad++ESP32-S3R16V from Espressif Systems, in a 56-VFQFN Exposed Pad. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | LNA_IN | bidirectional | RF low-noise amplifier input/output signal pin. |+| 2 | VDD3P3 | power_in | Analog power domain supply pin. |+| 3 | VDD3P3 | power_in | Analog power domain supply pin. |+| 4 | CHIP_PU | input | High enables the chip and low disables it; the datasheet says this pin must not be left floating. |+| 5 | GPIO0 | bidirectional | General-purpose I/O with internal weak pull-up at reset; strapping pin for chip boot mode control. |+| 6 | GPIO1 | bidirectional | General-purpose I/O with ADC1_CH0 and TOUCH1 analog functions; shows a low-level glitch of about 60 µs at power-up. |+| 7 | GPIO2 | bidirectional | General-purpose I/O with ADC1_CH1 and TOUCH2 analog functions; shows a low-level glitch of about 60 µs at power-up. |+| 8 | GPIO3 | bidirectional | General-purpose I/O with ADC1_CH2 and TOUCH3 analog functions; floating at reset and used as a strapping pin for JTAG signal source selection. |+| 9 | GPIO4 | bidirectional | General-purpose I/O with ADC1_CH3 and TOUCH4 analog functions; shows a low-level glitch of about 60 µs at power-up. |+| 10 | GPIO5 | bidirectional | General-purpose I/O with ADC1_CH4 and TOUCH5 analog functions; shows a low-level glitch of about 60 µs at power-up. |+| 11 | GPIO6 | bidirectional | General-purpose I/O with ADC1_CH5 and TOUCH6 analog functions; shows a low-level glitch of about 60 µs at power-up. |+| 12 | GPIO7 | bidirectional | General-purpose I/O with ADC1_CH6 and TOUCH7 analog functions; shows a low-level glitch of about 60 µs at power-up. |+| 13 | GPIO8 | bidirectional | General-purpose I/O with ADC1_CH7 and TOUCH8 analog functions; shows a low-level glitch of about 60 µs at power-up. |+| 14 | GPIO9 | bidirectional | General-purpose I/O with ADC1_CH8 and TOUCH9 analog functions; shows a low-level glitch of about 60 µs at power-up. |+| 15 | GPIO10 | bidirectional | General-purpose I/O with ADC1_CH9 and TOUCH10 analog functions; shows a low-level glitch of about 60 µs at power-up. |+| 16 | GPIO11 | bidirectional | General-purpose I/O with ADC2_CH0 and TOUCH11 analog functions; shows a low-level glitch of about 60 µs at power-up. |+| 17 | GPIO12 | bidirectional | General-purpose I/O with ADC2_CH1 and TOUCH12 analog functions; shows a low-level glitch of about 60 µs at power-up. |+| 18 | GPIO13 | bidirectional | General-purpose I/O with ADC2_CH2 and TOUCH13 analog functions; shows a low-level glitch of about 60 µs at power-up. |+| 19 | GPIO14 | bidirectional | General-purpose I/O with ADC2_CH3 and TOUCH14 analog functions; shows a low-level glitch of about 60 µs at power-up. |+| 20 | VDD3P3_RTC | power_in | Power input for the RTC domain and part of the digital domain, which powers the RTC IO pins. |+| 21 | XTAL_32K_P | bidirectional | Positive terminal of the 32 kHz external clock oscillator; also general-purpose I/O RTC_GPIO15 with ADC2_CH4 and U0RTS. |+| 22 | XTAL_32K_N | bidirectional | Negative terminal of the 32 kHz external clock oscillator; also general-purpose I/O RTC_GPIO16 with ADC2_CH5 and U0CTS. |+| 23 | GPIO17 | bidirectional | General-purpose I/O with ADC2_CH6 and U1TXD; default drive strength is 10 mA. |+| 24 | GPIO18 | bidirectional | General-purpose I/O with ADC2_CH7 and U1RXD; default drive strength is 10 mA. |+| 25 | GPIO19 | bidirectional | General-purpose I/O, also USB_D- for the USB Serial/JTAG and USB OTG functions; default drive strength is 40 mA. |+| 26 | GPIO20 | bidirectional | General-purpose I/O, also USB_D+ for the USB Serial/JTAG and USB OTG functions; default drive strength is 40 mA. |+| 27 | GPIO21 | bidirectional | General-purpose I/O powered by VDD3P3_RTC with RTC_GPIO21 function. |+| 28 | SPICS1 | bidirectional | SPI chip select 1 for in-package PSRAM (GPIO26); powered by VDD_SPI, which is 1.8 V on R16V, and must not be used for other purposes. |+| 29 | VDD_SPI | power_out | Power pin for in-package memory and SPI IO; set to 1.8 V on the ESP32-S3R16V. |+| 30 | SPIHD | bidirectional | SPI hold signal for in-package flash/PSRAM (GPIO27) with internal weak pull-up at reset; powered by VDD_SPI. |+| 31 | SPIWP | bidirectional | SPI write-protect signal for in-package flash/PSRAM (GPIO28) with internal weak pull-up at reset; powered by VDD_SPI. |+| 32 | SPICS0 | bidirectional | SPI chip select 0 for in-package flash (GPIO29) with internal weak pull-up at reset; powered by VDD_SPI. |+| 33 | SPICLK | bidirectional | SPI clock for in-package flash/PSRAM (GPIO30) with internal weak pull-up at reset; powered by VDD_SPI. |+| 34 | SPIQ | bidirectional | SPI data line for in-package flash/PSRAM (GPIO31) with internal weak pull-up at reset; powered by VDD_SPI. |+| 35 | SPID | bidirectional | SPI data line for in-package flash/PSRAM (GPIO32) with internal weak pull-up at reset; powered by VDD_SPI. |+| 36 | SPICLK_N | bidirectional | Negative differential SPI clock (GPIO48) for in-package memory; at 1.8 V on R16V because VDD_SPI is 1.8 V. |+| 37 | SPICLK_P | bidirectional | Positive differential SPI clock (GPIO47) for in-package memory; at 1.8 V on R16V because VDD_SPI is 1.8 V. |+| 38 | GPIO33 | bidirectional | General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the high 4-bit data line for 8-line SPI mode when in-package Octal PSRAM is connected. |+| 39 | GPIO34 | bidirectional | General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQ5 data line for in-package Octal PSRAM. |+| 40 | GPIO35 | bidirectional | General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQ6 data line for in-package Octal PSRAM. |+| 41 | GPIO36 | bidirectional | General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQ7 data line for in-package Octal PSRAM. |+| 42 | GPIO37 | bidirectional | General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQS/DM strobe for in-package Octal PSRAM. |+| 43 | GPIO38 | bidirectional | General-purpose I/O powered by VDD3P3_CPU with FSPIWP and SUBSPIWP alternate functions. |+| 44 | MTCK | bidirectional | JTAG test clock (GPIO39) powered by VDD3P3_CPU; its weak pull-up depends on EFUSE_DIS_PAD_JTAG. |+| 45 | MTDO | bidirectional | JTAG test data output (GPIO40) powered by VDD3P3_CPU. |+| 46 | VDD3P3_CPU | power_in | Digital power domain supply for the digital IO pins. |+| 47 | MTDI | bidirectional | JTAG test data input (GPIO41) powered by VDD3P3_CPU. |+| 48 | MTMS | bidirectional | JTAG test mode select (GPIO42) powered by VDD3P3_CPU. |+| 49 | U0TXD | bidirectional | UART0 transmit data (GPIO43) with internal weak pull-up at reset; powered by VDD3P3_CPU. |+| 50 | U0RXD | bidirectional | UART0 receive data (GPIO44) with internal weak pull-up at reset; powered by VDD3P3_CPU. |+| 51 | GPIO45 | bidirectional | General-purpose I/O with internal weak pull-down at reset; strapping pin for VDD_SPI voltage control. |+| 52 | GPIO46 | bidirectional | General-purpose I/O with internal weak pull-down at reset; strapping pin for chip boot mode and ROM message printing control. |+| 53 | XTAL_N | passive | Negative terminal of the external clock input/output connected to the chip's crystal or oscillator. |+| 54 | XTAL_P | passive | Positive terminal of the external clock input/output connected to the chip's crystal or oscillator. |+| 55 | VDDA | power_in | Analog power domain supply pin. |+| 56 | VDDA | power_in | Analog power domain supply pin. |+| 57 | GND | power_in | Ground; the exposed pad of the QFN56 package is the external ground connection. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Espressif Systems |+| Package | 56-VFQFN Exposed Pad |+| Category | RF and Wireless |+| Pins | 57 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Allowed input voltage (input power pins) | | -0.3 | | 3.6 | V | | 64 |+| Cumulative IO output current | Ioutput | | | 1500 | mA | | 64 |+| Storage temperature | TSTORE | -40 | | 150 | °C | | 64 |+| Recommended input voltage | VDDA, VDD3P3 | 3 | 3.3 | 3.6 | V | | 64 |+| Recommended input voltage | VDD_SPI (as input) | 1.8 | 3.3 | 3.6 | V | | 64 |+| Cumulative input current | IVDD | 0.5 | | | A | | 64 |+| ESD HBM (Human Body Model) | | -2000 | | 2000 | V | HBM, JS-001 | 69 |+| ESD CDM (Charge Device Model) | | -1000 | | 1000 | V | CDM, JS-002 | 69 |+| Latch-up current trigger | | -200 | | 200 | mA | JESD78, current trigger | 69 |+| Low-level input voltage | VIL | -0.3 | | | V | | 65 |+| Chip reset voltage | VIL_nRST | -0.3 | | | V | CHIP_PU voltage is within the specified range | 65 |+| High-level input current | IIH | | | 50 | nA | | 65 |+| Low-level input current | IIL | | | 50 | nA | | 65 |+| Pin capacitance | CIN | | 2 | | pF | | 65 |+| High-level source current | IOH | | 40 | | mA | VDD = 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3 | 65 |+| Low-level sink current | IOL | | 28 | | mA | VDD = 3.3 V, VOL = 0.495 V, PAD_DRIVER = 3 | 65 |+| Internal weak pull-up resistor | RPU | | 45 | | kΩ | | 65 |+| Internal weak pull-down resistor | RPD | | 45 | | kΩ | | 65 |+| VDD_SPI powered by VDD3P3_RTC via RSPI | RSPI | | 14 | | Ω | for 3.3 V flash/PSRAM | 65 |+| Output current when VDD_SPI powered by Flash Voltage Regulator | ISPI | | 40 | | mA | for 1.8 V flash/PSRAM | 65 |+| Differential nonlinearity | DNL | -4 | | 4 | LSB | external 100 nF capacitor on ADC, 25 °C, Wi-Fi disabled | 66 |+| Integral nonlinearity | INL | -8 | | 8 | LSB | external 100 nF capacitor on ADC, 25 °C, Wi-Fi disabled | 66 |+| ADC sampling rate | | | | 100 | kSPS | | 66 |+| ADC total error ATTEN0 | | -5 | | 5 | mV | effective measurement range 0 ~ 850 | 66 |+| ADC total error ATTEN1 | | -6 | | 6 | mV | effective measurement range 0 ~ 1100 | 66 |+| ADC total error ATTEN2 | | -10 | | 10 | mV | effective measurement range 0 ~ 1600 | 66 |+| ADC total error ATTEN3 | | -50 | | 50 | mV | effective measurement range 0 ~ 2900 | 66 |+| Wi-Fi TX peak current 802.11b | | | | 340 | mA | 802.11b, 1 Mbps, @21 dBm; 3.3 V, 25 °C | 66 |+| Wi-Fi TX peak current 802.11g | | | | 291 | mA | 802.11g, 54 Mbps, @19 dBm; 3.3 V, 25 °C | 66 |+| Wi-Fi TX peak current 802.11n HT20 | | | | 283 | mA | 802.11n, HT20, MCS7, @18.5 dBm; 3.3 V, 25 °C | 66 |+| Wi-Fi TX peak current 802.11n HT40 | | | | 286 | mA | 802.11n, HT40, MCS7, @18 dBm; 3.3 V, 25 °C | 66 |+| Wi-Fi RX peak current 802.11b/g/n HT20 | | | | 88 | mA | 802.11b/g/n, HT20; 3.3 V, 25 °C | 66 |+| Wi-Fi RX peak current 802.11n HT40 | | | | 91 | mA | 802.11n, HT40; 3.3 V, 25 °C | 66 |+| Bluetooth LE TX peak current | | | | 335 | mA | Bluetooth LE @ 21.0 dBm; 3.3 V, 25 °C | 67 |+| Bluetooth LE TX peak current | | | | 176 | mA | Bluetooth LE @ 0 dBm; 3.3 V, 25 °C | 67 |+| Bluetooth LE RX peak current | | | | 93 | mA | Bluetooth LE; 3.3 V, 25 °C | 67 |+| Light-sleep current | | | 240 | | µA | VDD_SPI and Wi-Fi powered down, all GPIOs high-impedance | 68 |+| Deep-sleep current, ULP co-processor on (ULP-FSM) | | | 170 | | µA | ULP co-processor powered on | 68 |+| Deep-sleep current, ULP co-processor on (ULP-RISC-V) | | | 190 | | µA | ULP co-processor powered on | 68 |+| Deep-sleep current, ULP sensor-monitored pattern | | | 18 | | µA | ULP sensor-monitored pattern | 68 |+| Deep-sleep current, RTC memory and RTC peripherals powered up | | | 8 | | µA | RTC memory and RTC peripherals powered up | 68 |+| Deep-sleep current, RTC memory powered up, RTC peripherals down | | | 7 | | µA | RTC memory powered up, RTC peripherals powered down | 68 |+| Power-off current | | | 1 | | µA | CHIP_PU set to low level | 68 |+| Flash power supply voltage (1.8 V) | VCC | 1.65 | 1.8 | 2 | V | Power supply voltage (1.8 V) | 68 |+| Flash maximum clock frequency | FC | 80 | | | MHz | | 68 |+| PSRAM power supply voltage (1.8 V) | VCC | 1.62 | 1.8 | 1.98 | V | Power supply voltage (1.8 V) | 69 |++## CAD (KiCad official)++- Symbol: `ESP32-S3R16V`+- Footprint: `Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm`+- 3D model: 56-VFQFN Exposed Pad (KiCad packages3D, STEP)+- 3D model files: `esp32-s3r16v-etched.step` / `esp32-s3r16v-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `esp32-s3r16v.step` / `esp32-s3r16v.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Espressif Systems datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf) (87 pp, sha256 `2d5a7cb7fd559d8d`, retrieved 2026-10-27, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/esp32-s3r16v-datasheet.pdf)
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esp32-s3r16v-hero.overlay.jsonadded+1329@@ -0,0 +1,1329 @@+{+ "spec": "adom-hero 1.4",+ "mpn": "ESP32-S3R16V",+ "kind": "component + footprint reference art",+ "board_use": false,+ "plane_z_mm": -0.02,+ "units": "metre",+ "upAxis": "Z",+ "layers": {+ "pad_outlines": {+ "material": "Footprint pads - teal dashed outlines - 50 percent opacity",+ "rgba": [+ 0.0,+ 0.902,+ 0.863,+ 0.5+ ],+ "pads": 57,+ "span_mm": 12.475,+ "dash_mm": 0.3119,+ "gap_mm": 0.1871,+ "pad_stroke_mm": 0.0748+ },+ "silkscreen": {+ "material": "Silkscreen reference lines - 30 percent opacity",+ "rgba": [+ 0.92,+ 0.96,+ 1.0,+ 0.3+ ],+ "footprint_items": 9,+ "pin1": {+ "source": "footprint silkscreen",+ "pad": "1"+ }+ },+ "signal_names": {+ "material": "Signal names - 50 percent opacity",+ "rgba": [+ 0.92,+ 0.96,+ 1.0,+ 0.5+ ],+ "font": "DejaVu Sans Mono",+ "labels": 56,+ "sides": "top + mirrored underside (single-sided)",+ "fallback_to_pad_number": 0+ }+ },+ "align": {+ "ok": true,+ "centre_offset_mm": 0.0,+ "tolerance_mm": 0.62,+ "orientation_flipped": false,+ "contacts_bbox_mm": [+ -3.5,+ 3.5,+ -3.5,+ 3.5+ ],+ "pads_bbox_mm": [+ -3.875,+ 3.875,+ -3.875,+ 3.875+ ],+ "seating_z_mm": -0.0+ },+ "sources": {+ "glb": "esp32-s3r16v-etched.glb",+ "glb_sha256": "e93eac6b9e3eff245929fd1474bd9c7414aeb493f63c64a1884282631f415633",+ "footprint": "esp32-s3r16v.kicad_mod",+ "footprint_sha256": "8d6e552da34a0837fc97fcdc1728c7388340d76107b165ddc5b3d42641f6dcd7",+ "pins": "page.json component.pins",+ "pins_sha256": "5f1c6d18b45407eb24c1271695c25a5398ee9f24fd3a327c827c1564080b602c"+ },+ "generator": "adom-wiki 1.8.0 (component_hero)",+ "labels": [+ {+ "pad": "1",+ "text": "LNA_IN",+ "x": -4.57,+ "y": -2.6,+ "align": "right",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "2",+ "text": "VDD3P3",+ "x": -3.975,+ "y": -2.2,+ "align": "right",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "3",+ "text": "VDD3P3",+ "x": -3.975,+ "y": -1.8,+ "align": "right",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "4",+ "text": "CHIP_PU",+ "x": -3.975,+ "y": -1.4,+ "align": "right",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "5",+ "text": "GPIO0",+ "x": -3.975,+ "y": -1.0,+ "align": "right",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "6",+ "text": "GPIO1",+ "x": -3.975,+ "y": -0.6,+ "align": "right",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "7",+ "text": "GPIO2",+ "x": -3.975,+ "y": -0.2,+ "align": "right",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "8",+ "text": "GPIO3",+ "x": -3.975,+ "y": 0.2,+ "align": "right",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "9",+ "text": "GPIO4",+ "x": -3.975,+ "y": 0.6,+ "align": "right",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "10",+ "text": "GPIO5",+ "x": -3.975,+ "y": 1.0,+ "align": "right",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "11",+ "text": "GPIO6",+ "x": -3.975,+ "y": 1.4,+ "align": "right",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "12",+ "text": "GPIO7",+ "x": -3.975,+ "y": 1.8,+ "align": "right",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "13",+ "text": "GPIO8",+ "x": -3.975,+ "y": 2.2,+ "align": "right",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "14",+ "text": "GPIO9",+ "x": -3.975,+ "y": 2.6,+ "align": "right",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "15",+ "text": "GPIO10",+ "x": -2.6,+ "y": 3.975,+ "align": "right",+ "vertical": true,+ "h": 0.2+ },+ {+ "pad": "16",+ "text": "GPIO11",+ "x": -2.2,+ "y": 3.975,+ "align": "right",+ "vertical": true,+ "h": 0.2+ },+ {+ "pad": "17",+ "text": "GPIO12",+ "x": -1.8,+ "y": 3.975,+ "align": "right",+ "vertical": true,+ "h": 0.2+ },+ {+ "pad": "18",+ "text": "GPIO13",+ "x": -1.4,+ "y": 3.975,+ "align": "right",+ "vertical": true,+ "h": 0.2+ },+ {+ "pad": "19",+ "text": "GPIO14",+ "x": -1.0,+ "y": 3.975,+ "align": "right",+ "vertical": true,+ "h": 0.2+ },+ {+ "pad": "20",+ "text": "VDD3P3_RTC",+ "x": -0.6,+ "y": 3.975,+ "align": "right",+ "vertical": true,+ "h": 0.2+ },+ {+ "pad": "21",+ "text": "XTAL_32K_P",+ "x": -0.2,+ "y": 3.975,+ "align": "right",+ "vertical": true,+ "h": 0.2+ },+ {+ "pad": "22",+ "text": "XTAL_32K_N",+ "x": 0.2,+ "y": 3.975,+ "align": "right",+ "vertical": true,+ "h": 0.2+ },+ {+ "pad": "23",+ "text": "GPIO17",+ "x": 0.6,+ "y": 3.975,+ "align": "right",+ "vertical": true,+ "h": 0.2+ },+ {+ "pad": "24",+ "text": "GPIO18",+ "x": 1.0,+ "y": 3.975,+ "align": "right",+ "vertical": true,+ "h": 0.2+ },+ {+ "pad": "25",+ "text": "GPIO19",+ "x": 1.4,+ "y": 3.975,+ "align": "right",+ "vertical": true,+ "h": 0.2+ },+ {+ "pad": "26",+ "text": "GPIO20",+ "x": 1.8,+ "y": 3.975,+ "align": "right",+ "vertical": true,+ "h": 0.2+ },+ {+ "pad": "27",+ "text": "GPIO21",+ "x": 2.2,+ "y": 3.975,+ "align": "right",+ "vertical": true,+ "h": 0.2+ },+ {+ "pad": "28",+ "text": "SPICS1",+ "x": 2.6,+ "y": 3.975,+ "align": "right",+ "vertical": true,+ "h": 0.2+ },+ {+ "pad": "29",+ "text": "VDD_SPI",+ "x": 3.975,+ "y": 2.6,+ "align": "left",+ "vertical": false,+ "h": 0.2+ },+ {+ "pad": "30",+ "text": "SPIHD",+ "x": 3.975,+ "y": 2.2,+ "align": "left",+ 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esp32-s3r16v.glbadded⋯ 1 unchanged line ⋯
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direction="pas"/>+ <pin name="GND" x="-39.37" y="53.34" length="middle" direction="pwr"/>+</symbol>+</symbols>+<devicesets>+<deviceset name="ESP32-S3R16V" prefix="U">+ <description>ESP32-S3 is a low-power MCU-based system-on-chip (SoC) that supports 2.4 GHz Wi-Fi and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor (Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, RF module, and peripherals</description>+ <gates>+ <gate name="G$1" symbol="ESP32-S3R16V" x="0" y="0"/>+ </gates>+ <devices>+ <device name="" package="QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm">+ <connects>+ <connect gate="G$1" pin="SPICLK_N/GPIO48" pad="36"/>+ <connect gate="G$1" pin="SPICLK_P/GPIO47" pad="37"/>+ <connect gate="G$1" pin="LNA_IN/RF" pad="1"/>+ <connect gate="G$1" pin="VDD3P3" pad="2"/>+ <connect gate="G$1" pin="VDD3P3@2" pad="3"/>+ <connect gate="G$1" pin="CHIP_PU/RESET" pad="4"/>+ <connect gate="G$1" pin="GPIO0/BOOT" pad="5"/>+ <connect gate="G$1" pin="GPIO1/ADC1_CH0" pad="6"/>+ <connect gate="G$1" pin="GPIO2/ADC1_CH1" pad="7"/>+ <connect gate="G$1" pin="GPIO3/ADC1_CH2" pad="8"/>+ <connect gate="G$1" pin="GPIO4/ADC1_CH3" pad="9"/>+ <connect gate="G$1" pin="GPIO5/ADC1_CH4" pad="10"/>+ <connect gate="G$1" pin="GPIO6/ADC1_CH5" pad="11"/>+ <connect gate="G$1" pin="GPIO7/ADC1_CH6" pad="12"/>+ <connect gate="G$1" pin="GPIO8/ADC1_CH7" pad="13"/>+ <connect gate="G$1" pin="GPIO9/ADC1_CH8" pad="14"/>+ <connect gate="G$1" pin="GPIO10/ADC1_CH9" pad="15"/>+ <connect gate="G$1" pin="GPIO11/ADC2_CH0" pad="16"/>+ <connect gate="G$1" pin="GPIO12/ADC2_CH1" pad="17"/>+ <connect gate="G$1" pin="GPIO13/ADC2_CH2" pad="18"/>+ <connect gate="G$1" pin="GPIO14/ADC2_CH3" pad="19"/>+ <connect gate="G$1" pin="VDD3P3_RTC" pad="20"/>+ <connect gate="G$1" pin="GPIO15/ADC2_CH4/XTAL_32K_P" pad="21"/>+ <connect gate="G$1" pin="GPIO16/ADC2_CH5/XTAL_32K_N" pad="22"/>+ <connect gate="G$1" pin="GPIO17/ADC2_CH6" pad="23"/>+ <connect gate="G$1" pin="GPIO18/ADC2_CH7" pad="24"/>+ <connect gate="G$1" pin="GPIO19/USB_D-/ADC2_CH8" pad="25"/>+ <connect gate="G$1" pin="GPIO20/USB_D+/ADC2_CH9" pad="26"/>+ <connect gate="G$1" pin="GPIO21" pad="27"/>+ <connect gate="G$1" pin="SPI_CS1/GPIO26" pad="28"/>+ <connect gate="G$1" pin="VDD_SPI" pad="29"/>+ <connect gate="G$1" pin="SPIHD/GPIO27" pad="30"/>+ <connect gate="G$1" pin="SPIWP/GPIO28" pad="31"/>+ <connect gate="G$1" pin="SPICS0/GPIO29" pad="32"/>+ <connect gate="G$1" pin="SPICLK/GPIO30" pad="33"/>+ <connect gate="G$1" pin="SPIQ/GPIO31" pad="34"/>+ <connect gate="G$1" pin="SPID/GPIO32" pad="35"/>+ <connect gate="G$1" pin="GPIO33" pad="38"/>+ <connect gate="G$1" pin="GPIO34" pad="39"/>+ <connect gate="G$1" pin="GPIO35" pad="40"/>+ <connect gate="G$1" pin="GPIO36" pad="41"/>+ <connect gate="G$1" pin="GPIO37" pad="42"/>+ <connect gate="G$1" pin="GPIO38" pad="43"/>+ <connect gate="G$1" pin="MTCK/JTAG/GPIO39" pad="44"/>+ <connect gate="G$1" pin="MTDO/JTAG/GPIO40" pad="45"/>+ <connect gate="G$1" pin="VDD3P3_CPU" pad="46"/>+ <connect gate="G$1" pin="MTDI/JTAG/GPIO41" pad="47"/>+ <connect gate="G$1" pin="MTMS/JTAG/GPIO42" pad="48"/>+ <connect gate="G$1" pin="U0TXD/PROG/GPIO43" pad="49"/>+ <connect gate="G$1" pin="U0RXD/PROG/GPIO44" pad="50"/>+ <connect gate="G$1" pin="GPIO45" pad="51"/>+ <connect gate="G$1" pin="GPIO46" pad="52"/>+ <connect gate="G$1" pin="XTAL_N" pad="53"/>+ <connect gate="G$1" pin="XTAL_P" pad="54"/>+ <connect gate="G$1" pin="VDDA" pad="55"/>+ <connect gate="G$1" pin="VDDA@2" pad="56"/>+ <connect gate="G$1" pin="GND" pad="57"/>+ </connects>+ <technologies><technology name=""/></technologies>+ </device>+ </devices>+</deviceset>+</devicesets>+</library>+</drawing>+</eagle>
esp32-s3r16v.stepadded+14216@@ -0,0 +1,14216 @@+ISO-10303-21; +HEADER; +/* QFN-56-1EP_7x7mm_Pitch0.4mm.step 3D STEP model for use in ECAD systems + * Copyright (C) 2017, kicad StepUp + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + * + * As a special exception, if you create a design which uses this symbol, + * and embed this symbol or unaltered portions of this symbol into the design, + * this symbol does not by itself cause the resulting design to be covered by + * the GNU General Public License. + * This exception does not however invalidate any other reasons why the design + * itself might be covered by the GNU General Public License. + * If you modify this symbol, you may extend this exception to your version of the symbol, + * but you are not obligated to do so. + * If you do not wish to do so, delete this exception statement from your version + * Risk disclaimer + * *USE 3D CAD DATA AT YOUR OWN RISK* + * *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.* + * + */ + +FILE_DESCRIPTION( +/* description */ ('model of QFN-56-1EP_7x7mm_Pitch0.4mm'), +/* implementation_level */ '2;1'); + +FILE_NAME( +/* name */ 'QFN-56-1EP_7x7mm_Pitch0.4mm.step', +/* time_stamp */ '2017-03-23T11:13:53', +/* author */ ('kicad StepUp','ksu'), +/* organization */ ('FreeCAD'), +/* preprocessor_version */ 'OCC', +/* originating_system */ 'kicad StepUp', +/* authorisation */ ''); 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package.jsonadded+487@@ -0,0 +1,487 @@+{+ "slug": "esp32-s3r16v",+ "version": "0.1.0",+ "type": "component",+ "description": "Espressif Systems RF and Wireless, 56-VFQFN Exposed Pad. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "rf and wireless",+ "esp32-s3r16v",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "esp32-s3r16v.kicad_sym",+ "esp32-s3r16v.kicad_mod",+ "esp32-s3r16v.glb",+ "esp32-s3r16v.step",+ "esp32-s3r16v.lbr",+ "docs/hero.png",+ "docs/esp32-s3r16v-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "esp32-s3r16v-hero.glb",+ "esp32-s3r16v-hero.overlay.json",+ "esp32-s3r16v-etched.glb"+ ],+ "component": {+ "mpn": "ESP32-S3R16V",+ "manufacturer": "Espressif Systems",+ "package": "56-VFQFN Exposed Pad",+ "pin_count": 57,+ "category": "RF and Wireless",+ "subcategory": "RF and Wireless",+ "datasheet": "https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf",+ "parts": {+ "symbol": "esp32-s3r16v.kicad_sym",+ "footprint": "esp32-s3r16v.kicad_mod",+ "model_3d": "esp32-s3r16v-hero.glb",+ "model_3d_plain": "esp32-s3r16v-etched.glb",+ "model_3d_step": "esp32-s3r16v-etched.step",+ "model_3d_step_plain": "esp32-s3r16v.step",+ "lbr": "esp32-s3r16v.lbr"+ },+ "distributor_links": {+ "mouser": "356-ESP32-S3R16V"+ },+ "distributor_check": {+ "checked_at": "2026-10-27T23:16:12Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "deferred",+ "error": "shared DigiKey quota guard: 968 calls left today"+ },+ "mouser": {+ "pn": "356-ESP32-S3R16V",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "LNA_IN",+ "type": "bidirectional",+ "description": "RF low-noise amplifier input/output signal pin."+ },+ {+ "number": "2",+ "name": "VDD3P3",+ "type": "power_in",+ "description": "Analog power domain supply pin."+ },+ {+ "number": "3",+ "name": "VDD3P3",+ "type": "power_in",+ "description": "Analog power domain supply pin."+ },+ {+ "number": "4",+ "name": "CHIP_PU",+ "type": "input",+ "description": "High enables the chip and low disables it; the datasheet says this pin must not be left floating."+ },+ {+ "number": "5",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "General-purpose I/O with internal weak pull-up at reset; strapping pin for chip boot mode control."+ },+ {+ "number": "6",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH0 and TOUCH1 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "7",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH1 and TOUCH2 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "8",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH2 and TOUCH3 analog functions; floating at reset and used as a strapping pin for JTAG signal source selection."+ },+ {+ "number": "9",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH3 and TOUCH4 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "10",+ "name": "GPIO5",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH4 and TOUCH5 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "11",+ "name": "GPIO6",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH5 and TOUCH6 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "12",+ "name": "GPIO7",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH6 and TOUCH7 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "13",+ "name": "GPIO8",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH7 and TOUCH8 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "14",+ "name": "GPIO9",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH8 and TOUCH9 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "15",+ "name": "GPIO10",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH9 and TOUCH10 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "16",+ "name": "GPIO11",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC2_CH0 and TOUCH11 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "17",+ "name": "GPIO12",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC2_CH1 and TOUCH12 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "18",+ "name": "GPIO13",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC2_CH2 and TOUCH13 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "19",+ "name": "GPIO14",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC2_CH3 and TOUCH14 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "20",+ "name": "VDD3P3_RTC",+ "type": "power_in",+ "description": "Power input for the RTC domain and part of the digital domain, which powers the RTC IO pins."+ },+ {+ "number": "21",+ "name": "XTAL_32K_P",+ "type": "bidirectional",+ "description": "Positive terminal of the 32 kHz external clock oscillator; also general-purpose I/O RTC_GPIO15 with ADC2_CH4 and U0RTS."+ },+ {+ "number": "22",+ "name": "XTAL_32K_N",+ "type": "bidirectional",+ "description": "Negative terminal of the 32 kHz external clock oscillator; also general-purpose I/O RTC_GPIO16 with ADC2_CH5 and U0CTS."+ },+ {+ "number": "23",+ "name": "GPIO17",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC2_CH6 and U1TXD; default drive strength is 10 mA."+ },+ {+ "number": "24",+ "name": "GPIO18",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC2_CH7 and U1RXD; default drive strength is 10 mA."+ },+ {+ "number": "25",+ "name": "GPIO19",+ "type": "bidirectional",+ "description": "General-purpose I/O, also USB_D- for the USB Serial/JTAG and USB OTG functions; default drive strength is 40 mA."+ },+ {+ "number": "26",+ "name": "GPIO20",+ "type": "bidirectional",+ "description": "General-purpose I/O, also USB_D+ for the USB Serial/JTAG and USB OTG functions; default drive strength is 40 mA."+ },+ {+ "number": "27",+ "name": "GPIO21",+ "type": "bidirectional",+ "description": "General-purpose I/O powered by VDD3P3_RTC with RTC_GPIO21 function."+ },+ {+ "number": "28",+ "name": "SPICS1",+ "type": "bidirectional",+ "description": "SPI chip select 1 for in-package PSRAM (GPIO26); powered by VDD_SPI, which is 1.8 V on R16V, and must not be used for other purposes."+ },+ {+ "number": "29",+ "name": "VDD_SPI",+ "type": "power_out",+ "description": "Power pin for in-package memory and SPI IO; set to 1.8 V on the ESP32-S3R16V."+ },+ {+ "number": "30",+ "name": "SPIHD",+ "type": "bidirectional",+ "description": "SPI hold signal for in-package flash/PSRAM (GPIO27) with internal weak pull-up at reset; powered by VDD_SPI."+ },+ {+ "number": "31",+ "name": "SPIWP",+ "type": "bidirectional",+ "description": "SPI write-protect signal for in-package flash/PSRAM (GPIO28) with internal weak pull-up at reset; powered by VDD_SPI."+ },+ {+ "number": "32",+ "name": "SPICS0",+ "type": "bidirectional",+ "description": "SPI chip select 0 for in-package flash (GPIO29) with internal weak pull-up at reset; powered by VDD_SPI."+ },+ {+ "number": "33",+ "name": "SPICLK",+ "type": "bidirectional",+ "description": "SPI clock for in-package flash/PSRAM (GPIO30) with internal weak pull-up at reset; powered by VDD_SPI."+ },+ {+ "number": "34",+ "name": "SPIQ",+ "type": "bidirectional",+ "description": "SPI data line for in-package flash/PSRAM (GPIO31) with internal weak pull-up at reset; powered by VDD_SPI."+ },+ {+ "number": "35",+ "name": "SPID",+ "type": "bidirectional",+ "description": "SPI data line for in-package flash/PSRAM (GPIO32) with internal weak pull-up at reset; powered by VDD_SPI."+ },+ {+ "number": "36",+ "name": "SPICLK_N",+ "type": "bidirectional",+ "description": "Negative differential SPI clock (GPIO48) for in-package memory; at 1.8 V on R16V because VDD_SPI is 1.8 V."+ },+ {+ "number": "37",+ "name": "SPICLK_P",+ "type": "bidirectional",+ "description": "Positive differential SPI clock (GPIO47) for in-package memory; at 1.8 V on R16V because VDD_SPI is 1.8 V."+ },+ {+ "number": "38",+ "name": "GPIO33",+ "type": "bidirectional",+ "description": "General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the high 4-bit data line for 8-line SPI mode when in-package Octal PSRAM is connected."+ },+ {+ "number": "39",+ "name": "GPIO34",+ "type": "bidirectional",+ "description": "General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQ5 data line for in-package Octal PSRAM."+ },+ {+ "number": "40",+ "name": "GPIO35",+ "type": "bidirectional",+ "description": "General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQ6 data line for in-package Octal PSRAM."+ },+ {+ "number": "41",+ "name": "GPIO36",+ "type": "bidirectional",+ "description": "General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQ7 data line for in-package Octal PSRAM."+ },+ {+ "number": "42",+ "name": "GPIO37",+ "type": "bidirectional",+ "description": "General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQS/DM strobe for in-package Octal PSRAM."+ },+ {+ "number": "43",+ "name": "GPIO38",+ "type": "bidirectional",+ "description": "General-purpose I/O powered by VDD3P3_CPU with FSPIWP and SUBSPIWP alternate functions."+ },+ {+ "number": "44",+ "name": "MTCK",+ "type": "bidirectional",+ "description": "JTAG test clock (GPIO39) powered by VDD3P3_CPU; its weak pull-up depends on EFUSE_DIS_PAD_JTAG."+ },+ {+ "number": "45",+ "name": "MTDO",+ "type": "bidirectional",+ "description": "JTAG test data output (GPIO40) powered by VDD3P3_CPU."+ },+ {+ "number": "46",+ "name": "VDD3P3_CPU",+ "type": "power_in",+ "description": "Digital power domain supply for the digital IO pins."+ },+ {+ "number": "47",+ "name": "MTDI",+ "type": "bidirectional",+ "description": "JTAG test data input (GPIO41) powered by VDD3P3_CPU."+ },+ {+ "number": "48",+ "name": "MTMS",+ "type": "bidirectional",+ "description": "JTAG test mode select (GPIO42) powered by VDD3P3_CPU."+ },+ {+ "number": "49",+ "name": "U0TXD",+ "type": "bidirectional",+ "description": "UART0 transmit data (GPIO43) with internal weak pull-up at reset; powered by VDD3P3_CPU."+ },+ {+ "number": "50",+ "name": "U0RXD",+ "type": "bidirectional",+ "description": "UART0 receive data (GPIO44) with internal weak pull-up at reset; powered by VDD3P3_CPU."+ },+ {+ "number": "51",+ "name": "GPIO45",+ "type": "bidirectional",+ "description": "General-purpose I/O with internal weak pull-down at reset; strapping pin for VDD_SPI voltage control."+ },+ {+ "number": "52",+ "name": "GPIO46",+ "type": "bidirectional",+ "description": "General-purpose I/O with internal weak pull-down at reset; strapping pin for chip boot mode and ROM message printing control."+ },+ {+ "number": "53",+ "name": "XTAL_N",+ "type": "passive",+ "description": "Negative terminal of the external clock input/output connected to the chip's crystal or oscillator."+ },+ {+ "number": "54",+ "name": "XTAL_P",+ "type": "passive",+ "description": "Positive terminal of the external clock input/output connected to the chip's crystal or oscillator."+ },+ {+ "number": "55",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power domain supply pin."+ },+ {+ "number": "56",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power domain supply pin."+ },+ {+ "number": "57",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; the exposed pad of the QFN56 package is the external ground connection."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet names the package QFN56 (7×7 mm) and lists 57 pin rows; pin 57 is GND, which is the ex; Pins 36 and 37 are inconsistent in the datasheet. Table 2-1 and Figure 2-1 name them SPICLK_N and SP; For ESP32-S3R16V, VDD_SPI is 1.8 V and the in-package 16 MB Octal SPI PSRAM uses pins 28-35 and 38-4"+ ],+ "pages_sent": 52,+ "cost_usd": 0.1843,+ "at": "2026-10-27T23:16:42"+ },+ "datasheet": {+ "url": "https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf",+ "pages": 87,+ "sha256": "2d5a7cb7fd559d8d",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 57,+ "described": 57,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "esp32-s3r16v.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7.0,+ 7.0,+ 0.92+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "a7e1b68d7c240016a0c468e633f7967f445758a90dea110c3eff24882158aaa8",+ "checked": "2026-10-27",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "esp32-s3r16v-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7.0,+ 7.0,+ 0.92+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "8945f414008607006e1a29fbfdb1f6f5df356a4253aa80778b95891d322f71be",+ "checked": "2026-10-27",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ }+}
page.jsonadded+493@@ -0,0 +1,493 @@+{+ "slug": "esp32-s3r16v",+ "version": "0.1.0",+ "type": "component",+ "description": "Espressif Systems RF and Wireless, 56-VFQFN Exposed Pad. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "rf and wireless",+ "esp32-s3r16v",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "esp32-s3r16v.kicad_sym",+ "esp32-s3r16v.kicad_mod",+ "esp32-s3r16v.glb",+ "esp32-s3r16v.step",+ "esp32-s3r16v.lbr",+ "docs/hero.png",+ "docs/esp32-s3r16v-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "esp32-s3r16v-hero.glb",+ "esp32-s3r16v-hero.overlay.json",+ "esp32-s3r16v-etched.glb"+ ],+ "component": {+ "mpn": "ESP32-S3R16V",+ "manufacturer": "Espressif Systems",+ "package": "56-VFQFN Exposed Pad",+ "pin_count": 57,+ "category": "RF and Wireless",+ "subcategory": "RF and Wireless",+ "datasheet": "https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf",+ "parts": {+ "symbol": "esp32-s3r16v.kicad_sym",+ "footprint": "esp32-s3r16v.kicad_mod",+ "model_3d": "esp32-s3r16v-hero.glb",+ "model_3d_plain": "esp32-s3r16v-etched.glb",+ "model_3d_step": "esp32-s3r16v-etched.step",+ "model_3d_step_plain": "esp32-s3r16v.step",+ "lbr": "esp32-s3r16v.lbr"+ },+ "distributor_links": {+ "mouser": "356-ESP32-S3R16V"+ },+ "distributor_check": {+ "checked_at": "2026-10-27T23:16:12Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "deferred",+ "error": "shared DigiKey quota guard: 968 calls left today"+ },+ "mouser": {+ "pn": "356-ESP32-S3R16V",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "LNA_IN",+ "type": "bidirectional",+ "description": "RF low-noise amplifier input/output signal pin."+ },+ {+ "number": "2",+ "name": "VDD3P3",+ "type": "power_in",+ "description": "Analog power domain supply pin."+ },+ {+ "number": "3",+ "name": "VDD3P3",+ "type": "power_in",+ "description": "Analog power domain supply pin."+ },+ {+ "number": "4",+ "name": "CHIP_PU",+ "type": "input",+ "description": "High enables the chip and low disables it; the datasheet says this pin must not be left floating."+ },+ {+ "number": "5",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "General-purpose I/O with internal weak pull-up at reset; strapping pin for chip boot mode control."+ },+ {+ "number": "6",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH0 and TOUCH1 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "7",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH1 and TOUCH2 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "8",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH2 and TOUCH3 analog functions; floating at reset and used as a strapping pin for JTAG signal source selection."+ },+ {+ "number": "9",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH3 and TOUCH4 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "10",+ "name": "GPIO5",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH4 and TOUCH5 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "11",+ "name": "GPIO6",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH5 and TOUCH6 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "12",+ "name": "GPIO7",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH6 and TOUCH7 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "13",+ "name": "GPIO8",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH7 and TOUCH8 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "14",+ "name": "GPIO9",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH8 and TOUCH9 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "15",+ "name": "GPIO10",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC1_CH9 and TOUCH10 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "16",+ "name": "GPIO11",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC2_CH0 and TOUCH11 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "17",+ "name": "GPIO12",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC2_CH1 and TOUCH12 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "18",+ "name": "GPIO13",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC2_CH2 and TOUCH13 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "19",+ "name": "GPIO14",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC2_CH3 and TOUCH14 analog functions; shows a low-level glitch of about 60 µs at power-up."+ },+ {+ "number": "20",+ "name": "VDD3P3_RTC",+ "type": "power_in",+ "description": "Power input for the RTC domain and part of the digital domain, which powers the RTC IO pins."+ },+ {+ "number": "21",+ "name": "XTAL_32K_P",+ "type": "bidirectional",+ "description": "Positive terminal of the 32 kHz external clock oscillator; also general-purpose I/O RTC_GPIO15 with ADC2_CH4 and U0RTS."+ },+ {+ "number": "22",+ "name": "XTAL_32K_N",+ "type": "bidirectional",+ "description": "Negative terminal of the 32 kHz external clock oscillator; also general-purpose I/O RTC_GPIO16 with ADC2_CH5 and U0CTS."+ },+ {+ "number": "23",+ "name": "GPIO17",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC2_CH6 and U1TXD; default drive strength is 10 mA."+ },+ {+ "number": "24",+ "name": "GPIO18",+ "type": "bidirectional",+ "description": "General-purpose I/O with ADC2_CH7 and U1RXD; default drive strength is 10 mA."+ },+ {+ "number": "25",+ "name": "GPIO19",+ "type": "bidirectional",+ "description": "General-purpose I/O, also USB_D- for the USB Serial/JTAG and USB OTG functions; default drive strength is 40 mA."+ },+ {+ "number": "26",+ "name": "GPIO20",+ "type": "bidirectional",+ "description": "General-purpose I/O, also USB_D+ for the USB Serial/JTAG and USB OTG functions; default drive strength is 40 mA."+ },+ {+ "number": "27",+ "name": "GPIO21",+ "type": "bidirectional",+ "description": "General-purpose I/O powered by VDD3P3_RTC with RTC_GPIO21 function."+ },+ {+ "number": "28",+ "name": "SPICS1",+ "type": "bidirectional",+ "description": "SPI chip select 1 for in-package PSRAM (GPIO26); powered by VDD_SPI, which is 1.8 V on R16V, and must not be used for other purposes."+ },+ {+ "number": "29",+ "name": "VDD_SPI",+ "type": "power_out",+ "description": "Power pin for in-package memory and SPI IO; set to 1.8 V on the ESP32-S3R16V."+ },+ {+ "number": "30",+ "name": "SPIHD",+ "type": "bidirectional",+ "description": "SPI hold signal for in-package flash/PSRAM (GPIO27) with internal weak pull-up at reset; powered by VDD_SPI."+ },+ {+ "number": "31",+ "name": "SPIWP",+ "type": "bidirectional",+ "description": "SPI write-protect signal for in-package flash/PSRAM (GPIO28) with internal weak pull-up at reset; powered by VDD_SPI."+ },+ {+ "number": "32",+ "name": "SPICS0",+ "type": "bidirectional",+ "description": "SPI chip select 0 for in-package flash (GPIO29) with internal weak pull-up at reset; powered by VDD_SPI."+ },+ {+ "number": "33",+ "name": "SPICLK",+ "type": "bidirectional",+ "description": "SPI clock for in-package flash/PSRAM (GPIO30) with internal weak pull-up at reset; powered by VDD_SPI."+ },+ {+ "number": "34",+ "name": "SPIQ",+ "type": "bidirectional",+ "description": "SPI data line for in-package flash/PSRAM (GPIO31) with internal weak pull-up at reset; powered by VDD_SPI."+ },+ {+ "number": "35",+ "name": "SPID",+ "type": "bidirectional",+ "description": "SPI data line for in-package flash/PSRAM (GPIO32) with internal weak pull-up at reset; powered by VDD_SPI."+ },+ {+ "number": "36",+ "name": "SPICLK_N",+ "type": "bidirectional",+ "description": "Negative differential SPI clock (GPIO48) for in-package memory; at 1.8 V on R16V because VDD_SPI is 1.8 V."+ },+ {+ "number": "37",+ "name": "SPICLK_P",+ "type": "bidirectional",+ "description": "Positive differential SPI clock (GPIO47) for in-package memory; at 1.8 V on R16V because VDD_SPI is 1.8 V."+ },+ {+ "number": "38",+ "name": "GPIO33",+ "type": "bidirectional",+ "description": "General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the high 4-bit data line for 8-line SPI mode when in-package Octal PSRAM is connected."+ },+ {+ "number": "39",+ "name": "GPIO34",+ "type": "bidirectional",+ "description": "General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQ5 data line for in-package Octal PSRAM."+ },+ {+ "number": "40",+ "name": "GPIO35",+ "type": "bidirectional",+ "description": "General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQ6 data line for in-package Octal PSRAM."+ },+ {+ "number": "41",+ "name": "GPIO36",+ "type": "bidirectional",+ "description": "General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQ7 data line for in-package Octal PSRAM."+ },+ {+ "number": "42",+ "name": "GPIO37",+ "type": "bidirectional",+ "description": "General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQS/DM strobe for in-package Octal PSRAM."+ },+ {+ "number": "43",+ "name": "GPIO38",+ "type": "bidirectional",+ "description": "General-purpose I/O powered by VDD3P3_CPU with FSPIWP and SUBSPIWP alternate functions."+ },+ {+ "number": "44",+ "name": "MTCK",+ "type": "bidirectional",+ "description": "JTAG test clock (GPIO39) powered by VDD3P3_CPU; its weak pull-up depends on EFUSE_DIS_PAD_JTAG."+ },+ {+ "number": "45",+ "name": "MTDO",+ "type": "bidirectional",+ "description": "JTAG test data output (GPIO40) powered by VDD3P3_CPU."+ },+ {+ "number": "46",+ "name": "VDD3P3_CPU",+ "type": "power_in",+ "description": "Digital power domain supply for the digital IO pins."+ },+ {+ "number": "47",+ "name": "MTDI",+ "type": "bidirectional",+ "description": "JTAG test data input (GPIO41) powered by VDD3P3_CPU."+ },+ {+ "number": "48",+ "name": "MTMS",+ "type": "bidirectional",+ "description": "JTAG test mode select (GPIO42) powered by VDD3P3_CPU."+ },+ {+ "number": "49",+ "name": "U0TXD",+ "type": "bidirectional",+ "description": "UART0 transmit data (GPIO43) with internal weak pull-up at reset; powered by VDD3P3_CPU."+ },+ {+ "number": "50",+ "name": "U0RXD",+ "type": "bidirectional",+ "description": "UART0 receive data (GPIO44) with internal weak pull-up at reset; powered by VDD3P3_CPU."+ },+ {+ "number": "51",+ "name": "GPIO45",+ "type": "bidirectional",+ "description": "General-purpose I/O with internal weak pull-down at reset; strapping pin for VDD_SPI voltage control."+ },+ {+ "number": "52",+ "name": "GPIO46",+ "type": "bidirectional",+ "description": "General-purpose I/O with internal weak pull-down at reset; strapping pin for chip boot mode and ROM message printing control."+ },+ {+ "number": "53",+ "name": "XTAL_N",+ "type": "passive",+ "description": "Negative terminal of the external clock input/output connected to the chip's crystal or oscillator."+ },+ {+ "number": "54",+ "name": "XTAL_P",+ "type": "passive",+ "description": "Positive terminal of the external clock input/output connected to the chip's crystal or oscillator."+ },+ {+ "number": "55",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power domain supply pin."+ },+ {+ "number": "56",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power domain supply pin."+ },+ {+ "number": "57",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; the exposed pad of the QFN56 package is the external ground connection."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet names the package QFN56 (7×7 mm) and lists 57 pin rows; pin 57 is GND, which is the ex; Pins 36 and 37 are inconsistent in the datasheet. Table 2-1 and Figure 2-1 name them SPICLK_N and SP; For ESP32-S3R16V, VDD_SPI is 1.8 V and the in-package 16 MB Octal SPI PSRAM uses pins 28-35 and 38-4"+ ],+ "pages_sent": 52,+ "cost_usd": 0.1843,+ "at": "2026-10-27T23:16:42"+ },+ "datasheet": {+ "url": "https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf",+ "pages": 87,+ "sha256": "2d5a7cb7fd559d8d",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 57,+ "described": 57,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "esp32-s3r16v.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.92+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "a7e1b68d7c240016a0c468e633f7967f445758a90dea110c3eff24882158aaa8",+ "checked": "2026-10-27",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "esp32-s3r16v-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.92+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "8945f414008607006e1a29fbfdb1f6f5df356a4253aa80778b95891d322f71be",+ "checked": "2026-10-27",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}
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