component
EF2M45LG48B
Public Made by Adomby adom
Anlogic Programmable Logic Device (CPLDs/FPGAs), LQFP-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+85@@ -0,0 +1,85 @@+# EF2M45LG48B++**Anlogic** · Programmable Logic Device (CPLDs/FPGAs) · LQFP-48-EP(7x7)++EF2M45LG48B from Anlogic, in a LQFP-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VCCAUX | power_in | Auxiliary power supply, nominal 2.5V with ±5% tolerance. |+| 2 | ADC_VDDA | power_in | ADC analog power supply at 3.3V; minimum 2.5V required for on-chip configuration. |+| 3 | ADC0_CH0,IO_L_0 | bidirectional | Analog-to-digital converter channel 0 input or general-purpose I/O with IOBE buffer in Bank 0. |+| 4 | PROGRAMN,IO_L1N_0 | bidirectional | Active-low asynchronous reset and configuration trigger input with internal pull-up to VCCIO. |+| 5 | JTAGEN,IO_L1P_0 | bidirectional | JTAG enable input (1=JTAG active, 0=JTAG pins become user I/O) with internal pull-up. |+| 6 | ADC0_CH1,GCLKIOL_1,LVDSRX_0N,IO_L2N_0 | bidirectional | ADC channel 1 input, global clock input, LVDS receiver negative differential pair, or Bank 0 user I/O. |+| 7 | ADC0_CH2,GCLKIOL_0,LVDSRX_0P,IO_L2P_0 | bidirectional | ADC channel 2 input, global clock input, LVDS receiver positive differential pair, or Bank 0 user I/O. |+| 8 | VCCIO_0 | power_in | User I/O Bank 0 power supply operating at 1.2V to 3.3V with peak-to-peak ripple <100mV. |+| 9 | ADC0_CH3,GCLKIOL_3,LVDSTX_0N,IO_L3N_0 | bidirectional | ADC channel 3 input, global clock input, LVDS transmitter negative differential pair, or Bank 0 user I/O. |+| 10 | ADC0_CH4,GCLKIOL_2,LVDSTX_0P,IO_L3P_0 | bidirectional | ADC channel 4 input, global clock input, LVDS transmitter positive differential pair, or Bank 0 user I/O. |+| 11 | TMS,IO_L4N_0 | bidirectional | JTAG test mode select input latched on TCK rising edge or Bank 0 user I/O with internal pull-up. |+| 12 | TCK,IO_L4P_0 | bidirectional | JTAG test clock with minimum 100ns period or Bank 0 user I/O with internal pull-up. |+| 13 | TDI,IO_L5N_0 | bidirectional | JTAG test data input latched on TCK rising edge or Bank 0 user I/O with internal pull-up. |+| 14 | TDO,IO_L5P_0 | bidirectional | JTAG test data output updated on TCK rising edge or Bank 0 user I/O. |+| 15 | D0,IO_BE1P_1 | bidirectional | Configuration data bit 0 during slave mode programming or Bank 1 user I/O after configuration. |+| 16 | D1,IO_BE1N_1 | bidirectional | Configuration data bit 1 during programming or Bank 1 user I/O after configuration. |+| 17 | VCCIO_1 | power_in | User I/O Bank 1 power supply, minimum 2.5V for Flash programming with peak-to-peak ripple <100mV. |+| 18 | D2,IO_BE2P_1 | bidirectional | Configuration data bit 2 during programming or Bank 1 user I/O after configuration. |+| 19 | D3,IO_BE2N_1 | bidirectional | Configuration data bit 3 during programming or Bank 1 user I/O after configuration. |+| 20 | VCCAUX | power_in | Auxiliary power supply, nominal 2.5V with ±5% tolerance for analog circuits. |+| 21 | D4,GCLKIOB_4,IO_BE3P_1 | bidirectional | Configuration data bit 4, global clock input buffer, or Bank 1 user I/O after configuration. |+| 22 | D5,GCLKIOB_5,IO_BE3N_1 | bidirectional | Configuration data bit 5, global clock input buffer, or Bank 1 user I/O after configuration. |+| 23 | VCCIO_1 | power_in | User I/O Bank 1 power supply, minimum 2.5V for Flash programming with peak-to-peak ripple <100mV. |+| 24 | D6,IO_BE4P_1 | bidirectional | Configuration data bit 6 during programming or Bank 1 user I/O after configuration. |+| 25 | D7,IO_BE4N_1 | bidirectional | Configuration data bit 7 during programming or Bank 1 user I/O after configuration. |+| 26 | IO_R1P_2 | bidirectional | Bank 2 user I/O with IOBE buffer, differential pair positive half for LVDS or single-ended operation. |+| 27 | IO_R1N_2 | bidirectional | Bank 2 user I/O with IOBE buffer, differential pair negative half for LVDS or single-ended operation. |+| 28 | IO_R1_2 | bidirectional | Bank 2 user I/O with IOBE buffer for single-ended or differential operation. |+| 29 | VCCIO_2 | power_in | User I/O Bank 2 power supply operating at 1.2V to 3.3V, minimum 2.5V when LVDS is used. |+| 30 | SCLK,IO_R2_2 | bidirectional | Configuration serial clock input (24MHz maximum) during programming or Bank 2 user I/O. |+| 31 | XTALI | input | Crystal oscillator input for on-chip ring oscillator, high impedance AC-coupled or direct crystal connection. |+| 32 | XTALO | output | Crystal oscillator output at 290MHz nominal (±30% tolerance) from on-chip ring oscillator. |+| 33 | VCCAUX | power_in | Auxiliary power supply, nominal 2.5V with ±5% tolerance for analog circuits. |+| 34 | GPIO4,IO_TE1N_3 | bidirectional | Bank 3 general-purpose I/O GPIO 4 with IOBB buffer, configuration data bit 4 negative differential half. |+| 35 | VBAT | power_in | Battery backup power supply for on-chip ring oscillator to maintain operation during system power loss. |+| 36 | GPIO3,IO_TE1P_3 | bidirectional | Bank 3 general-purpose I/O GPIO 3 with IOBB buffer, configuration data bit 4 positive differential half. |+| 37 | GPIO13,IO_TE2N_3 | bidirectional | Bank 3 general-purpose I/O GPIO 13 with IOBB buffer, configuration data bit 5 negative differential half. |+| 38 | GPIO12,IO_TE2P_3 | bidirectional | Bank 3 general-purpose I/O GPIO 12 with IOBB buffer, configuration data bit 5 positive differential half. |+| 39 | GPIO11,IO_TE3N_3 | bidirectional | Bank 3 general-purpose I/O GPIO 11 with IOBB buffer, configuration data bit 6 negative differential half. |+| 40 | GPIO10,IO_TE3P_3 | bidirectional | Bank 3 general-purpose I/O GPIO 10 with IOBB buffer, configuration data bit 6 positive differential half. |+| 41 | GPIO9,DPCLKIO_7,ADC1_CH3,IO_TE4N_3 | bidirectional | Bank 3 general-purpose I/O GPIO 9, digital clock I/O, ADC channel 3 input, or configuration differential pair. |+| 42 | GPIO8,USRCLK,ADC1_CH2,IO_TE4P_3 | bidirectional | Bank 3 general-purpose I/O GPIO 8, user system clock input, ADC channel 2 input, or configuration differential pair. |+| 43 | GPIO7,ADC1_CH1,IO_T1_3 | bidirectional | Bank 3 general-purpose I/O GPIO 7 or ADC channel 1 input with shared IOBB buffer. |+| 44 | GPIO6,DPCLKIO_8,ADC1_CH0,IO_T2_3 | bidirectional | Bank 3 general-purpose I/O GPIO 6, digital clock I/O, or ADC channel 0 input with IOBB buffer. |+| 45 | GPIO5,ADC0_VREF,IO_T3_3 | bidirectional | Bank 3 general-purpose I/O GPIO 5 or ADC0 reference voltage input operating at 0.5V to 1.0×VDDA. |+| 46 | GPIO0,ADC1_CH4,IO_TE5P_3 | bidirectional | Bank 3 general-purpose I/O GPIO 0, ADC channel 4 input, or configuration data bit 7 positive differential half. |+| 47 | GPIO1,ADC1_VREF,IO_TE5N_3 | bidirectional | Bank 3 general-purpose I/O GPIO 1, ADC1 reference voltage input (0.5V to 1.0×VDDA), or configuration data bit 7 negative half. |+| 48 | VCCIO_3 | power_in | User I/O Bank 3 power supply operating at 1.2V to 3.3V, minimum 2.5V for Flash programming. |+| 49 | GND_EPAD | power_in | Power ground connection for exposed pad on package bottom surface, must connect to main ground plane. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Anlogic |+| Package | LQFP-48-EP(7x7) |+| Category | Embedded Processors & Controllers |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `EF2M45LG48B`+- Footprint: `Package_QFP:LQFP-48-1EP_7x7mm_P0.5mm_EP3.6x3.6mm`+- 3D model: LQFP-48-EP(7x7) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Anlogic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603176760037027840) (121 pp, sha256 `e95db5f86a1d297b`, retrieved 2026-09-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ef2m45lg48b-datasheet.pdf)
page.jsonadded+384@@ -0,0 +1,384 @@+{+ "slug": "ef2m45lg48b",+ "version": "0.1.0",+ "type": "component",+ "description": "Anlogic Programmable Logic Device (CPLDs/FPGAs), LQFP-48-EP(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "ef2m45lg48b",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ef2m45lg48b.kicad_sym",+ "ef2m45lg48b.kicad_mod",+ "ef2m45lg48b.glb",+ "ef2m45lg48b.step",+ "ef2m45lg48b.lbr",+ "docs/hero.png",+ "docs/ef2m45lg48b-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "EF2M45LG48B",+ "manufacturer": "Anlogic",+ "package": "LQFP-48-EP(7x7)",+ "pin_count": 49,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Programmable Logic Device (CPLDs/FPGAs)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603176760037027840",+ "parts": {+ "symbol": "ef2m45lg48b.kicad_sym",+ "footprint": "ef2m45lg48b.kicad_mod",+ "model_3d": "ef2m45lg48b.glb",+ "model_3d_step": "ef2m45lg48b.step",+ "lbr": "ef2m45lg48b.lbr"+ },+ "distributor_links": {+ "lcsc": "C5360148"+ },+ "pins": [+ {+ "number": "1",+ "name": "VCCAUX",+ "type": "power_in",+ "description": "Auxiliary power supply, nominal 2.5V with ±5% tolerance."+ },+ {+ "number": "2",+ "name": "ADC_VDDA",+ "type": "power_in",+ "description": "ADC analog power supply at 3.3V; minimum 2.5V required for on-chip configuration."+ },+ {+ "number": "3",+ "name": "ADC0_CH0,IO_L_0",+ "type": "bidirectional",+ "description": "Analog-to-digital converter channel 0 input or general-purpose I/O with IOBE buffer in Bank 0."+ },+ {+ "number": "4",+ "name": "PROGRAMN,IO_L1N_0",+ "type": "bidirectional",+ "description": "Active-low asynchronous reset and configuration trigger input with internal pull-up to VCCIO."+ },+ {+ "number": "5",+ "name": "JTAGEN,IO_L1P_0",+ "type": "bidirectional",+ "description": "JTAG enable input (1=JTAG active, 0=JTAG pins become user I/O) with internal pull-up."+ },+ {+ "number": "6",+ "name": "ADC0_CH1,GCLKIOL_1,LVDSRX_0N,IO_L2N_0",+ "type": "bidirectional",+ "description": "ADC channel 1 input, global clock input, LVDS receiver negative differential pair, or Bank 0 user I/O."+ },+ {+ "number": "7",+ "name": "ADC0_CH2,GCLKIOL_0,LVDSRX_0P,IO_L2P_0",+ "type": "bidirectional",+ "description": "ADC channel 2 input, global clock input, LVDS receiver positive differential pair, or Bank 0 user I/O."+ },+ {+ "number": "8",+ "name": "VCCIO_0",+ "type": "power_in",+ "description": "User I/O Bank 0 power supply operating at 1.2V to 3.3V with peak-to-peak ripple <100mV."+ },+ {+ "number": "9",+ "name": "ADC0_CH3,GCLKIOL_3,LVDSTX_0N,IO_L3N_0",+ "type": "bidirectional",+ "description": "ADC channel 3 input, global clock input, LVDS transmitter negative differential pair, or Bank 0 user I/O."+ },+ {+ "number": "10",+ "name": "ADC0_CH4,GCLKIOL_2,LVDSTX_0P,IO_L3P_0",+ "type": "bidirectional",+ "description": "ADC channel 4 input, global clock input, LVDS transmitter positive differential pair, or Bank 0 user I/O."+ },+ {+ "number": "11",+ "name": "TMS,IO_L4N_0",+ "type": "bidirectional",+ "description": "JTAG test mode select input latched on TCK rising edge or Bank 0 user I/O with internal pull-up."+ },+ {+ "number": "12",+ "name": "TCK,IO_L4P_0",+ "type": "bidirectional",+ "description": "JTAG test clock with minimum 100ns period or Bank 0 user I/O with internal pull-up."+ },+ {+ "number": "13",+ "name": "TDI,IO_L5N_0",+ "type": "bidirectional",+ "description": "JTAG test data input latched on TCK rising edge or Bank 0 user I/O with internal pull-up."+ },+ {+ "number": "14",+ "name": "TDO,IO_L5P_0",+ "type": "bidirectional",+ "description": "JTAG test data output updated on TCK rising edge or Bank 0 user I/O."+ },+ {+ "number": "15",+ "name": "D0,IO_BE1P_1",+ "type": "bidirectional",+ "description": "Configuration data bit 0 during slave mode programming or Bank 1 user I/O after configuration."+ },+ {+ "number": "16",+ "name": "D1,IO_BE1N_1",+ "type": "bidirectional",+ "description": "Configuration data bit 1 during programming or Bank 1 user I/O after configuration."+ },+ {+ "number": "17",+ "name": "VCCIO_1",+ "type": "power_in",+ "description": "User I/O Bank 1 power supply, minimum 2.5V for Flash programming with peak-to-peak ripple <100mV."+ },+ {+ "number": "18",+ "name": "D2,IO_BE2P_1",+ "type": "bidirectional",+ "description": "Configuration data bit 2 during programming or Bank 1 user I/O after configuration."+ },+ {+ "number": "19",+ "name": "D3,IO_BE2N_1",+ "type": "bidirectional",+ "description": "Configuration data bit 3 during programming or Bank 1 user I/O after configuration."+ },+ {+ "number": "20",+ "name": "VCCAUX",+ "type": "power_in",+ "description": "Auxiliary power supply, nominal 2.5V with ±5% tolerance for analog circuits."+ },+ {+ "number": "21",+ "name": "D4,GCLKIOB_4,IO_BE3P_1",+ "type": "bidirectional",+ "description": "Configuration data bit 4, global clock input buffer, or Bank 1 user I/O after configuration."+ },+ {+ "number": "22",+ "name": "D5,GCLKIOB_5,IO_BE3N_1",+ "type": "bidirectional",+ "description": "Configuration data bit 5, global clock input buffer, or Bank 1 user I/O after configuration."+ },+ {+ "number": "23",+ "name": "VCCIO_1",+ "type": "power_in",+ "description": "User I/O Bank 1 power supply, minimum 2.5V for Flash programming with peak-to-peak ripple <100mV."+ },+ {+ "number": "24",+ "name": "D6,IO_BE4P_1",+ "type": "bidirectional",+ "description": "Configuration data bit 6 during programming or Bank 1 user I/O after configuration."+ },+ {+ "number": "25",+ "name": "D7,IO_BE4N_1",+ "type": "bidirectional",+ "description": "Configuration data bit 7 during programming or Bank 1 user I/O after configuration."+ },+ {+ "number": "26",+ "name": "IO_R1P_2",+ "type": "bidirectional",+ "description": "Bank 2 user I/O with IOBE buffer, differential pair positive half for LVDS or single-ended operation."+ },+ {+ "number": "27",+ "name": "IO_R1N_2",+ "type": "bidirectional",+ "description": "Bank 2 user I/O with IOBE buffer, differential pair negative half for LVDS or single-ended operation."+ },+ {+ "number": "28",+ "name": "IO_R1_2",+ "type": "bidirectional",+ "description": "Bank 2 user I/O with IOBE buffer for single-ended or differential operation."+ },+ {+ "number": "29",+ "name": "VCCIO_2",+ "type": "power_in",+ "description": "User I/O Bank 2 power supply operating at 1.2V to 3.3V, minimum 2.5V when LVDS is used."+ },+ {+ "number": "30",+ "name": "SCLK,IO_R2_2",+ "type": "bidirectional",+ "description": "Configuration serial clock input (24MHz maximum) during programming or Bank 2 user I/O."+ },+ {+ "number": "31",+ "name": "XTALI",+ "type": "input",+ "description": "Crystal oscillator input for on-chip ring oscillator, high impedance AC-coupled or direct crystal connection."+ },+ {+ "number": "32",+ "name": "XTALO",+ "type": "output",+ "description": "Crystal oscillator output at 290MHz nominal (±30% tolerance) from on-chip ring oscillator."+ },+ {+ "number": "33",+ "name": "VCCAUX",+ "type": "power_in",+ "description": "Auxiliary power supply, nominal 2.5V with ±5% tolerance for analog circuits."+ },+ {+ "number": "34",+ "name": "GPIO4,IO_TE1N_3",+ "type": "bidirectional",+ "description": "Bank 3 general-purpose I/O GPIO 4 with IOBB buffer, configuration data bit 4 negative differential half."+ },+ {+ "number": "35",+ "name": "VBAT",+ "type": "power_in",+ "description": "Battery backup power supply for on-chip ring oscillator to maintain operation during system power loss."+ },+ {+ "number": "36",+ "name": "GPIO3,IO_TE1P_3",+ "type": "bidirectional",+ "description": "Bank 3 general-purpose I/O GPIO 3 with IOBB buffer, configuration data bit 4 positive differential half."+ },+ {+ "number": "37",+ "name": "GPIO13,IO_TE2N_3",+ "type": "bidirectional",+ "description": "Bank 3 general-purpose I/O GPIO 13 with IOBB buffer, configuration data bit 5 negative differential half."+ },+ {+ "number": "38",+ "name": "GPIO12,IO_TE2P_3",+ "type": "bidirectional",+ "description": "Bank 3 general-purpose I/O GPIO 12 with IOBB buffer, configuration data bit 5 positive differential half."+ },+ {+ "number": "39",+ "name": "GPIO11,IO_TE3N_3",+ "type": "bidirectional",+ "description": "Bank 3 general-purpose I/O GPIO 11 with IOBB buffer, configuration data bit 6 negative differential half."+ },+ {+ "number": "40",+ "name": "GPIO10,IO_TE3P_3",+ "type": "bidirectional",+ "description": "Bank 3 general-purpose I/O GPIO 10 with IOBB buffer, configuration data bit 6 positive differential half."+ },+ {+ "number": "41",+ "name": "GPIO9,DPCLKIO_7,ADC1_CH3,IO_TE4N_3",+ "type": "bidirectional",+ "description": "Bank 3 general-purpose I/O GPIO 9, digital clock I/O, ADC channel 3 input, or configuration differential pair."+ },+ {+ "number": "42",+ "name": "GPIO8,USRCLK,ADC1_CH2,IO_TE4P_3",+ "type": "bidirectional",+ "description": "Bank 3 general-purpose I/O GPIO 8, user system clock input, ADC channel 2 input, or configuration differential pair."+ },+ {+ "number": "43",+ "name": "GPIO7,ADC1_CH1,IO_T1_3",+ "type": "bidirectional",+ "description": "Bank 3 general-purpose I/O GPIO 7 or ADC channel 1 input with shared IOBB buffer."+ },+ {+ "number": "44",+ "name": "GPIO6,DPCLKIO_8,ADC1_CH0,IO_T2_3",+ "type": "bidirectional",+ "description": "Bank 3 general-purpose I/O GPIO 6, digital clock I/O, or ADC channel 0 input with IOBB buffer."+ },+ {+ "number": "45",+ "name": "GPIO5,ADC0_VREF,IO_T3_3",+ "type": "bidirectional",+ "description": "Bank 3 general-purpose I/O GPIO 5 or ADC0 reference voltage input operating at 0.5V to 1.0×VDDA."+ },+ {+ "number": "46",+ "name": "GPIO0,ADC1_CH4,IO_TE5P_3",+ "type": "bidirectional",+ "description": "Bank 3 general-purpose I/O GPIO 0, ADC channel 4 input, or configuration data bit 7 positive differential half."+ },+ {+ "number": "47",+ "name": "GPIO1,ADC1_VREF,IO_TE5N_3",+ "type": "bidirectional",+ "description": "Bank 3 general-purpose I/O GPIO 1, ADC1 reference voltage input (0.5V to 1.0×VDDA), or configuration data bit 7 negative half."+ },+ {+ "number": "48",+ "name": "VCCIO_3",+ "type": "power_in",+ "description": "User I/O Bank 3 power supply operating at 1.2V to 3.3V, minimum 2.5V for Flash programming."+ },+ {+ "number": "49",+ "name": "GND_EPAD",+ "type": "power_in",+ "description": "Power ground connection for exposed pad on package bottom surface, must connect to main ground plane."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 121,+ "cost_usd": 1.1579,+ "at": "2026-09-17T17:20:14"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603176760037027840",+ "pages": 121,+ "sha256": "e95db5f86a1d297b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}