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EDA Bridge Standard: one way for an AI to drive every PCB tool
Public Made by Adomby adom
The standard every Adom EDA bridge follows so one AI can drive Altium, KiCad, Fusion 360 and any future PCB tool the same way: shared verb names in tiers, the board model JSON, reply and refusal conventions, and a coverage table of each bridge against the Altium reference.
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altium-lane: reference/altium-0.2.76.json updated (232 verbs: export_odb, export_ipc2581). Not regenerated: standard-lane regenerates
1 file changed
+69−3
reference/altium-0.2.76.json+69−3@@ -4141,6 +4141,7 @@ "Anti-aliasing differs between tool versions: rendererChanged:true means drift may not be a design change.", "A baseline is per sheet and per width; a paper size change reads as 100 percent drift.", "Altium prints the sheet to PDF (through its project when one beside it lists the sheet) and Windows renders it.",+ "Windows scales the image by the display's scale factor; the bridge asks again to correct it, so width is within a pixel of the one asked (800 px is 799 at 150%): compare uses the baseline's own size.", "Altium's print now and then leaves the title block's special strings (=Title, sheet numbers) unfilled; a failed comparison prints once more and keeps the closer image (reprinted:true), so drift confined to the title block is usually that." ], "related": [@@ -4432,6 +4433,70 @@ "summary": "Remove board graphics (lines, rectangles, circles, arcs, polygons, texts, dimensions) by id, or every one on a layer and of a kind. One undo step.", "timeoutSeconds": 300 },+ {+ "example": {+ "filePath": "C:/proj/Board.PcbDoc"+ },+ "hint": "Send the archive to a fab that takes ODB++ instead of Gerbers. export_manufacturing makes the Gerber set.",+ "input": {+ "compression": "zip|tgz|none, default zip",+ "filePath": "path to the board file (default: the board open in the tool)",+ "outputDir": "folder for the output (default beside the board)",+ "units": "mm|in, default mm"+ },+ "longRunning": false,+ "name": "altium_export_odb",+ "output": {+ "files": "[path]",+ "outputDir": "path"+ },+ "pitfalls": [+ "Run run_drc first: the file carries the board's errors with it.",+ "Altium writes it with its manufacturing template's settings: units, compression and version options are reported under optionsNotApplied.",+ "The board must be a document of a .PrjPcb in its folder."+ ],+ "related": [+ "altium_export_manufacturing",+ "altium_run_drc"+ ],+ "statusVerb": null,+ "summary": "Export the board as ODB++ (copper, drill, stack-up, netlist and parts in one archive) through the tool's own exporter.",+ "timeoutSeconds": 600+ },+ {+ "example": {+ "bomFields": {+ "mpn": "MPN"+ },+ "filePath": "C:/proj/Board.PcbDoc"+ },+ "hint": "Name the part fields with bomFields, or the BOM inside the file carries no part numbers.",+ "input": {+ "bomFields": "{mpn, manufacturer, distributorPn, distributor}: the part field names that carry these, so the embedded BOM is useful to the fab",+ "compress": "bool, default false: zip the XML",+ "filePath": "path to the board file (default: the board open in the tool)",+ "outputDir": "folder for the output (default beside the board)",+ "units": "mm|in, default mm",+ "version": "B|C, default C"+ },+ "longRunning": false,+ "name": "altium_export_ipc2581",+ "output": {+ "file": "path"+ },+ "pitfalls": [+ "Run run_drc first: the file carries the board's errors with it.",+ "Altium writes it with its manufacturing template's settings: units, compression and version options are reported under optionsNotApplied.",+ "The board must be a document of a .PrjPcb in its folder."+ ],+ "related": [+ "altium_export_manufacturing",+ "altium_run_drc"+ ],+ "statusVerb": null,+ "summary": "Export the board as IPC-2581: one XML file with copper, drill, stack-up, netlist and BOM, through the tool's own exporter.",+ "timeoutSeconds": 600+ }, { "example": { "connections": [@@ -5511,12 +5576,13 @@ "example": { "fab": "jlcpcb" },- "hint": "Look up the fab's own limits (its capability page) and pass them: the bridge does not carry fab numbers, they change. The measured values are what a fab's order form asks for.",+ "hint": "Computed by the EDA Bridge Standard's shared engine (adom-eda-checks). Fab limits come from adom/pcb-design-rules' records, bundled with the bridge: each finding names the vendor's page and the date it was read. limits adds or overrides any limit. The measured values are what a fab's order form asks for.", "input": { "copperOz": "outer copper weight for the preset (default: read from the stack)",- "fab": "jlcpcb - JLCPCB's published standard capabilities for this board's layer count and copper weight (source and date in the reply)",+ "fab": "a vendor adom/pcb-design-rules covers (jlcpcb, pcbway, osh-park, eurocircuits, aisler, allpcb, elecrow, nextpcb, seeed-fusion, advanced-circuits-4pcb, sierra-circuits, macrofab, adom-3rdpartyfab): its record for this board's layer count (source page and date read in the reply); or a record object from that page", "filePath": "the .PcbDoc (opened first)",- "limits": "{minTrack, minClearance, minViaDrill, minViaDiameter, minViaAnnularRing, minPadHole, minPadAnnularRing, minSmdPad, minEdgeClearance, minHoleToHoleVia, minHoleToHolePad, maxDrill, minSilkLine, minSilkText, maxLayers, minBoardMm:[w,h], maxBoardMm:[w,h]} in mm - any fab's numbers; with fab, these override the preset"+ "limits": "{minTrack, minClearance, minViaDrill, minViaDiameter, minViaAnnularRing, minPadHole, minPadAnnularRing, minSmdPad, minEdgeClearance, minHoleToHoleVia, minHoleToHolePad, maxDrill, minSilkLine, minSilkText, maxLayers, minBoardMm:[w,h], maxBoardMm:[w,h]} in mm - any fab's numbers; with fab, these override the preset",+ "process": "the record's process (default standard)" }, "longRunning": false, "name": "altium_fab_check",