EDA Bridge Standard: one way for an AI to drive every PCB tool

@@ -1,17 +1,17 @@ # Coverage: every standard verb on each bridge -Altium bridge 0.2.89 (the reference), KiCad bridge 1.0.98, Fusion 360 bridge 1.13.55. 100 verbs came from other bridges' proposals (tools/proposed/); they are marked *proposed*.+Altium bridge 0.2.89 (the reference), KiCad bridge 1.0.98, Fusion 360 bridge 1.13.59. 100 verbs came from other bridges' proposals (tools/proposed/); they are marked *proposed*. `exact` is the same job under the same or an equivalent name; `partial` does part of it or does it differently (`verbs/coverage.json` names what in `note`); `unsupported` answers `not_supported` for the whole job and is not counted; blank is missing. Generated by `tools/generate.py` from `verbs/coverage.json`; do not edit by hand.  | Tier | Verbs | Altium | KiCad | Fusion 360 | |---|---|---|---|---|-| **core** | 99 | 95 | 99 | 93 |-| **native** | 55 | 53 | 54 | 51 |-| **checks** | 39 | 38 | 39 | 38 |-| **app** | 70 | 66 | 57 | 61 |+| **core** | 99 | 95 | 99 | 96 |+| **native** | 55 | 53 | 54 | 52 |+| **checks** | 39 | 38 | 39 | 39 |+| **app** | 70 | 66 | 57 | 62 | | **platform** | 40 | 18 | 0 | 23 |-| standard (all but platform) | 263 | 252 | 249 | 243 |+| standard (all but platform) | 263 | 252 | 249 | 249 |  ## core @@ -55,7 +55,7 @@ Read and edit the design. Every bridge provides these: they are how an AI sees a | `part_parameters` | The parameter names a project's parts carry (with how many parts carry each), or with name, that parameter's value on every part. | `altium_part_parameters` | `kicad_part_parameters` | `fusion_part_parameters` | | `place_on_pcb` | Place ONE footprint from a PcbLib on a new board and return a proof frame. The single-part predecessor of altium_test_board. | `altium_place_on_pcb` | `kicad_place_footprint / kicad_add_footprint` | `fusion_test_board` (partial) | | `place_on_sch` | Place one symbol, or a ';' list of symbols, from the open SchLib on ONE new sheet (sheet sized FROM the measured parts: 500 mil gaps, 600 mil margins, A4... | `altium_place_on_sch` | `kicad_place_on_sch` | `fusion_make_showcase_project` (partial) |-| `place_parts` *proposed* | Put footprints from a library onto the current board, each with its position, rotation and side, and read them back. One undo step. |  | `kicad_add_footprint` (partial) |  |+| `place_parts` *proposed* | Put footprints from a library onto the current board, each with its position, rotation and side, and read them back. One undo step. |  | `kicad_add_footprint` (partial) | `fusion_place_parts` (partial) | | `place_vias` | Place vias (through, top to bottom). One undo step, read back. | `altium_place_vias` | `kicad_add_via` | `fusion_place_vias` | | `plate_vias` | Make every drilled pad in a PcbLib a plated MULTI-LAYER pad (all footprints, or footprintName). adom-lbr writes heatsink vias as pads with a hole; Altium... | `altium_plate_vias` | `kicad_plate_vias` | `fusion_plate_vias` | | `project_create` *proposed* | Create a new project folder with a project file, an empty schematic and an empty board (2 to 32 copper layers), with a title and text variables. | `altium_project_create` | `kicad_project_create` | `fusion_project_create` (partial) |@@ -91,9 +91,9 @@ Read and edit the design. Every bridge provides these: they are how an AI sees a | `sch_hierarchy` *proposed* | The sheet tree of a design, recursively: each sheet's name, file, id, instance path, page number, position, size and pins. renumber:true renumbers pages... | `altium_sch_hierarchy` | `kicad_sch_hierarchy` | `fusion_sch_hierarchy` (partial) | | `sch_items` *proposed* | List a sheet's wiring items with ids and coordinates: wires, buses, bus entries, net labels (local, global, hierarchical), power ports, junctions,... | `altium_sch_items` | `kicad_sch_items` | `fusion_sch_items` | | `sch_junction` *proposed* | Add junction dots at points, or remove dots by id or point. One undo step. | `altium_sch_junction` | `kicad_sch_junction` | `fusion_sch_junction` |-| `sch_label` *proposed* | Put a net label on an existing wire at a point, or delete one. sch_connect labels a pin through a new stub, and sch_edit_label changes labels that already... |  | `kicad_sch_label` |  |+| `sch_label` *proposed* | Put a net label on an existing wire at a point, or delete one. sch_connect labels a pin through a new stub, and sch_edit_label changes labels that already... |  | `kicad_sch_label` | `fusion_sch_label` (partial) | | `sch_move_region` *proposed* | Move everything inside a box by (dx, dy): parts, wire ends inside the box (wires crossing its edge stretch), labels, junctions, no-connect markers, texts,... | `altium_sch_move_region` | `kicad_sch_move_region` | `fusion_sch_move_region` |-| `sch_no_connect` *proposed* | Put a no-connect marker on a sheet, at a point or on a pin, or remove one by its sch_items id. One undo step. |  | `kicad_sch_no_connect` |  |+| `sch_no_connect` *proposed* | Put a no-connect marker on a sheet, at a point or on a pin, or remove one by its sch_items id. One undo step. |  | `kicad_sch_no_connect` | unsupported | | `sch_page` *proposed* | Read or set a sheet's page: paper size, orientation and title block (title, date, revision, company, comment lines). | `altium_sch_page` | `kicad_sch_page` | `fusion_sch_page` (partial) | | `sch_pins` *proposed* | Every pin of the named parts on a sheet: its absolute position (rotation and mirror applied), number, name, electrical type, the side it leaves the body,... | `altium_sch_pins` | `kicad_sch_pins` | `fusion_sch_pins` | | `sch_place_part` | Place a component from a .SchLib onto an EXISTING sheet at a position, with its library parameters (MPN, Manufacturer, distributor numbers) and its... | `altium_sch_place_part` | `kicad_sch_place_part` | `fusion_sch_place_part` |@@ -104,7 +104,7 @@ Read and edit the design. Every bridge provides these: they are how an AI sees a | `sch_swap_part` | Replace a placed part with another library part (a different value, package or symbol) at the same place, designator and rotation, keeping its connections:... | `altium_sch_swap_part` | `kicad_sch_swap_part` | `fusion_sch_swap_part` | | `sch_text` *proposed* | Add free text to a sheet (a note, a title, a design comment) with size, angle, justification, bold and italic. Text has no electrical meaning. One undo step. | `altium_sch_text` | `kicad_sch_text` | `fusion_sch_text` | | `sch_trace_point` *proposed* | Everything electrically connected at a point on a sheet: the wires, labels, pins, junctions, sheet pins and no-connect markers there, and for each net they... | `altium_sch_trace_point` | `kicad_sch_trace_point` | `fusion_sch_trace_point` |-| `sch_wire` *proposed* | Draw a wire through given points on a sheet, in the same units as the other sch_* wiring verbs. One undo step. |  | `kicad_sch_wire` |  |+| `sch_wire` *proposed* | Draw a wire through given points on a sheet, in the same units as the other sch_* wiring verbs. One undo step. |  | `kicad_sch_wire` | `fusion_sch_wire` | | `schematic_data` | Components on a schematic sheet (filePath, else the CURRENT sheet) with their pins (number, name, electrical type), position and orientation. designator... | `altium_schematic_data` | `kicad_sch_components` (partial) | `fusion_schematic_data` (partial) | | `set_layer_count` *proposed* | Set the board's copper layer count (2, 4, 6 or 8): the layer table and the stack-up, keeping the board thickness. | `altium_set_layer_count` | `kicad_set_layer_count` | `fusion_set_layer_count` | | `set_models` | Replace every footprint model on a SchLib component with ONE PCBLIB model (set_params footprint and add_models APPEND, which is how a symbol ends up with two). | `altium_set_models` | `kicad_footprint_models` (partial) | `fusion_set_models` |@@ -136,7 +136,7 @@ Wraps the EDA tool's own feature (its DRC, ERC, Gerbers, pours, Update PCB). Eve | `create_part_project` *proposed* | Generate a small real project (schematic and board) around one library part, so the part can be shown and tested in every view: schematic, 2D board and 3D... | `altium_create_part_project` | `kicad_create_part_project` (partial) | `fusion_make_test_project` (partial) | | `diff_pairs` | Differential pairs on the current board: list them, define one from two nets (replacing a pair of that name), or remove one. Altium's differential-pair... | `altium_diff_pairs` | `kicad_diff_pairs` (partial) | `fusion_diff_pairs` (partial) | | `edit_pours` *proposed* | Change existing pours in place without redrawing them: clearance, minimum width, thermal relief (on/off, spoke width, gap), priority or rank, the net, and... | `altium_edit_pours` | `kicad_edit_pours` | `fusion_edit_pours` (partial) |-| `edit_tracks` *proposed* | Change given tracks by the handle routing_state returns: width, layer and ends. One undo step, read back. |  | `kicad_modify_track` (partial) |  |+| `edit_tracks` *proposed* | Change given tracks by the handle routing_state returns: width, layer and ends. One undo step, read back. |  | `kicad_modify_track` (partial) | `fusion_edit_tracks` (partial) | | `export_3d` *proposed* | Export the board's 3D model in a mesh or CAD format other than STEP (export_step has STEP), through the tool's own exporter, with an optional web-optimized... | `altium_export_3d` | `kicad_export_3d` | `fusion_export_3d` | | `export_bom` | Bill of materials export: altium_run_outjob with the assembly OutJob and the 'Folder Structure' medium as defaults. | `altium_export_bom` | `kicad_export_bom` | `fusion_export_bom` | | `export_dxf` *proposed* | Export chosen board layers to DXF, one file per layer (the outline, panel drawings, stencils, enclosure work). | `altium_export_dxf` | `kicad_export_dxf` | `fusion_export_dxf` |@@ -210,7 +210,7 @@ Engineering computed from the board model, not by the tool: one shared engine, s | `jlcpcb_order` | A JLCPCB order in one call: the board checked against JLCPCB's fab limits, the Gerbers and drill zipped the way JLCPCB's order page takes them, the JLCPCB... | `altium_jlcpcb_order` | `kicad_jlcpcb_order` | `fusion_jlcpcb_order` | | `length_tune` | Lengthen a routed net to a target length, or to match another net (a pair's skew, a DDR byte lane): a serpentine in its longest straight track that has room... | `altium_length_tune` | `kicad_length_tune` | `fusion_length_tune` | | `lint_library` | Check a .PcbLib or .SchLib before it ships: footprints without pads, courtyard, silkscreen or 3D body, with duplicate or missing pad numbers, an origin off... | `altium_lint_library` | `kicad_lint_library` | `fusion_lint_library` |-| `model_check` *proposed* | Per part: is there a 3D model, where is it, is the file found, and does it hold geometry. For a library footprint or a whole board. Read only. |  | `kicad_model_check` |  |+| `model_check` *proposed* | Per part: is there a 3D model, where is it, is the file found, and does it hold geometry. For a library footprint or a whole board. Read only. |  | `kicad_model_check` | `fusion_model_check` (partial) | | `net_lengths` | Routed length of every net (or the ones named) on the live board, by layer with its vias; the skew inside each differential pair; and the spread of... | `altium_net_lengths` | `kicad_net_lengths` | `fusion_net_lengths` | | `pin_pad_check` | Do the footprints fit their symbols? Part by part, the symbol's pin numbers (from the sheet files) against the footprint's pad names (from the board): pins... | `altium_pin_pad_check` | `kicad_pin_pad_check` | `fusion_pin_pad_check` | | `place_decoupling` *proposed* | Plan positions for decoupling capacitors beside an IC's power pins (each cap just outside the courtyard, its power pad facing the pin), answered as... | `altium_place_decoupling` | `kicad_place_decoupling` | `fusion_place_decoupling` |@@ -256,7 +256,7 @@ Driving the application itself (launch, licence, dialogs, windows, views). Each | `eval` | Run a DelphiScript snippet inside Altium (optional Var block, then Begin ... End;) on the CURRENT document, or on filePath opened first. | `altium_eval` | `kicad_eval` | `fusion_run_modeling_script` (partial) | | `export_spice` *proposed* | Write the design's SPICE netlist with the tool's own exporter, and say what it holds. | `altium_export_spice` | `kicad_export_spice` | `fusion_export_spice` | | `extension_ping` | Does the AdomBridge .NET extension answer? Sends AdomBridge:Ping through the -R lane and waits up to 30 s for its result file. | `altium_extension_ping` | unsupported | `fusion_addin_status` (partial) |-| `extensions` *proposed* | The tool's own plugins and add-ons: list what is installed, install one, remove one. Not install_extension, which is the bridge's own helper inside the tool. |  | `kicad_pcm_list / kicad_pcm_install / kicad_pcm_uninstall` (partial) |  |+| `extensions` *proposed* | The tool's own plugins and add-ons: list what is installed, install one, remove one. Not install_extension, which is the bridge's own helper inside the tool. |  | `kicad_pcm_list / kicad_pcm_install / kicad_pcm_uninstall` (partial) | `fusion_extensions` (partial) | | `foreground` | Bring Altium in front of the user - the sanctioned exception to the never-foreground rule. | `altium_foreground` | `kicad_foreground` | `fusion_foreground` | | `install` | Install Altium Designer on this machine, STAGED, with the rules in the verb (from 0.2.29). stage: preflight / get_installer / launch / wait / license, or... | `altium_install` | `kicad_upgrade` (partial) | `fusion_install` | | `install_extension` | Install, update or remove the AdomBridge .NET extension (the PowerShell installer shipped beside the bridge). Altium must be CLOSED. | `altium_install_extension` | unsupported | unsupported |

@@ -1,5 +1,5 @@ {- "standard": "0.31.3",+ "standard": "0.31.4",  "reference": {   "bridge": "altium",   "version": "0.2.89"@@ -7,7 +7,7 @@  "proposed": 100,  "compared": {   "kicad": "1.0.98",-  "fusion360": "1.13.55"+  "fusion360": "1.13.59"  },  "tiers": {   "core": "Read and edit the design. Every bridge provides these: they are how an AI sees and changes a board.",@@ -652,7 +652,11 @@     "match": "partial",     "note": "one footprint or one row per call, not a parts list; the verb under the standard's name is coming"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_place_parts",+    "match": "partial",+    "note": "a board with no schematic, position, rotation and side, read back; nets are not taken; a board linked to a schematic is refused (linked_board), since Fusion takes its parts from the sheet (sch_place_part, then move_parts)"+   }   },   {    "name": "place_vias",@@ -1266,7 +1270,11 @@     "verb": "kicad_sch_label",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_sch_label",+    "match": "partial",+    "note": "a label on an existing wire at a point, and delete one; kind global is an XREF label, and hierarchical is refused (Fusion has no such label); text must name the wire's net, since a label shows its wire's net (renaming is sch_edit_label)"+   }   },   {    "name": "sch_move_region",@@ -1294,7 +1302,11 @@     "verb": "kicad_sch_no_connect",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_not_supported",+    "match": "unsupported",+    "note": "Fusion has no no-connect marker: its text commands have none (checked live on 2706), and an EAGLE pin is marked unused by its direction in the library. Leave the pin open and approve its ERC message"+   }   },   {    "name": "sch_page",@@ -1482,7 +1494,11 @@     "verb": "kicad_sch_wire",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_sch_wire",+    "match": "exact",+    "note": "Fusion names a wire's net: net names it, else it takes the net it starts on, else a free name; save is false by default (each Fusion save is a cloud version)"+   }   },   {    "name": "schematic_data",@@ -1918,7 +1934,11 @@     "match": "partial",     "note": "the standard's tracks list is KiCad's changes list; the verb under the standard's name is coming"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_edit_tracks",+    "match": "partial",+    "note": "width and layer; an end moves only along the track's own line, since Fusion's MOVE bends an angled move into two segments, which is undone and refused (end_move_bends); ids are the track's net, layer and ends, as Fusion stores none"+   }   },   {    "name": "export_3d",@@ -3072,7 +3092,11 @@     "verb": "kicad_model_check",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_model_check",+    "match": "partial",+    "note": "Fusion's models are cloud 3D packages: found means the file opens for this account; hasGeometry is null, as Fusion can't say without opening each one"+   }   },   {    "name": "net_lengths",@@ -3450,7 +3474,7 @@    "fusion360": {     "verb": "fusion_cancel_run",     "match": "partial",-    "note": "library imports (fusion_create_library, fusion_install_library_bundle): the only long jobs that stop between steps"+    "note": "library imports (fusion_create_library, fusion_install_library_bundle): the bridge's only long jobs that stop between steps"    }   },   {@@ -3746,7 +3770,11 @@     "match": "partial",     "note": "three verbs for KiCad's Plugin and Content Manager; one verb under the standard's name is coming"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_extensions",+    "match": "partial",+    "note": "lists the add-ins and scripts installed for this user; install and remove refused, as Fusion has no API; no update feed"+   }   },   {    "name": "foreground",@@ -4008,7 +4036,7 @@    "fusion360": {     "verb": "fusion_preferences",     "match": "exact",-    "note": "Fusion's appearance and navigation settings, applied live with no restart"+    "note": "Fusion's appearance and navigation settings, applied live with no restart, so tool_running does not arise"    }   },   {@@ -4146,7 +4174,7 @@    "fusion360": {     "verb": "fusion_select_items",     "match": "partial",-    "note": "parts by designator in the editor in front, or in the one where names; verified is always false, since Fusion does not report its electronics selection back"+    "note": "parts by designator in the editor in front, and where is refused when the other editor is in front; verified is always false, since Fusion does not report its electronics selection back"    }   },   {