EDA Bridge Standard: one way for an AI to drive every PCB tool

@@ -28,7 +28,7 @@   "partial"  ],  "move_parts": [-  "move_footprint",+  "move_footprint / flip_footprint",   "exact"  ],  "net_connections": [@@ -44,7 +44,7 @@   "partial"  ],  "place_on_pcb": [-  "place_footprint",+  "place_footprint / add_footprint",   "exact"  ],  "place_vias": [@@ -52,7 +52,7 @@   "exact"  ],  "placement_check": [-  "placement_validate",+  "placement_validate / score_placement",   "partial"  ],  "pour_state": [@@ -160,11 +160,11 @@   "exact"  ],  "footprint_primitives": [-  "fp_info",+  "footprint_graphics",   "partial"  ],  "selection": [-  "get_selection",+  "get_selection / select_items",   "exact"  ],  "save": [@@ -206,5 +206,57 @@  "open_document": [   "open_board / open_schematic",   "partial"+ ],+ "set_models": [+  "footprint_models",+  "partial"+ ],+ "add_models": [+  "footprint_models",+  "partial"+ ],+ "select_net": [+  "select_clear",+  "partial"+ ],+ "render_board_3d": [+  "render_board",+  "exact"+ ],+ "render_board_layers": [+  "export_svg",+  "partial"+ ],+ "remove_parts": [+  "delete_footprint",+  "exact"+ ],+ "edit_parts": [+  "edit_footprint",+  "exact"+ ],+ "align_parts": [+  "align_footprints",+  "exact"+ ],+ "remove_graphics": [+  "delete_graphics",+  "exact"+ ],+ "read_footprint": [+  "fp_info",+  "exact"+ ],+ "edit_footprint": [+  "fp_edit",+  "exact"+ ],+ "export_library_part": [+  "export_part",+  "partial"+ ],+ "create_part_project": [+  "make_part_project",+  "partial"  ] }

@@ -920,5 +920,1071 @@   "agreedBy": [    "altium-lane"   ]+ },+ {+  "name": "export_odb",+  "tier": "native",+  "summary": "Export the board as ODB++ (copper, drill, stack-up, netlist and parts in one archive) through the tool's own exporter.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "outputDir": "folder for the output (default beside the board)",+   "units": "mm|in, default mm",+   "compression": "zip|tgz|none, default zip"+  },+  "output": {+   "files": "[path]",+   "outputDir": "path"+  },+  "hint": "Send the archive to a fab that takes ODB++ instead of Gerbers. export_manufacturing makes the Gerber set.",+  "pitfalls": [+   "Run run_drc first: the file carries the board's errors with it."+  ],+  "related": [+   "export_manufacturing",+   "export_ipc2581",+   "run_drc"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc"+  },+  "longRunning": true,+  "timeoutSeconds": 300,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "export_ipc2581",+  "tier": "native",+  "summary": "Export the board as IPC-2581: one XML file with copper, drill, stack-up, netlist and BOM, through the tool's own exporter.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "outputDir": "folder for the output (default beside the board)",+   "version": "B|C, default C",+   "units": "mm|in, default mm",+   "compress": "bool, default false: zip the XML",+   "bomFields": "{mpn, manufacturer, distributorPn, distributor}: the part field names that carry these, so the embedded BOM is useful to the fab"+  },+  "output": {+   "file": "path"+  },+  "hint": "Name the part fields with bomFields, or the BOM inside the file carries no part numbers.",+  "pitfalls": [+   "Run run_drc first: the file carries the board's errors with it."+  ],+  "related": [+   "export_odb",+   "export_manufacturing",+   "run_drc"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "bomFields": {+    "mpn": "MPN"+   }+  },+  "longRunning": true,+  "timeoutSeconds": 300,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "export_ipc356",+  "tier": "native",+  "summary": "Export the IPC-D-356 netlist of the board, for bare-board electrical test (flying probe or bed of nails).",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "outputDir": "folder for the output (default beside the board)"+  },+  "output": {+   "file": "path"+  },+  "hint": "Send it with the Gerbers when the fab tests boards against the netlist.",+  "pitfalls": [+   "Run run_drc first: the file carries the board's errors with it."+  ],+  "related": [+   "export_manufacturing",+   "netlist"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc"+  },+  "longRunning": true,+  "timeoutSeconds": 300,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "export_gencad",+  "tier": "native",+  "summary": "Export the board as GenCAD 1.4, the input of test-fixture tools and some assembly houses' CAM.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "outputDir": "folder for the output (default beside the board)",+   "uniquePins": "bool, default false: rename duplicate pad numbers (several fixture tools need it)",+   "flipBottomPads": "bool, default false",+   "useDrillOrigin": "bool, default false: coordinates from the drill origin instead of the board's origin"+  },+  "output": {+   "file": "path"+  },+  "hint": "Ask the fixture or assembly house which options it needs; uniquePins is the common one.",+  "pitfalls": [+   "Run run_drc first: the file carries the board's errors with it."+  ],+  "related": [+   "export_manufacturing",+   "export_ipc356"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "uniquePins": true+  },+  "longRunning": true,+  "timeoutSeconds": 300,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "export_dxf",+  "tier": "native",+  "summary": "Export chosen board layers to DXF, one file per layer (the outline, panel drawings, stencils, enclosure work).",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "layers": "[\"Edge.Cuts\", \"F.Cu\"]: layer names (required; there is no sensible default)",+   "outputDir": "folder for the output (default beside the board)",+   "units": "mm|in, default mm",+   "contours": "bool, default false: join outline segments into polylines (most CAM and laser tools want it)",+   "titleBlock": "bool, default false",+   "excludeDesignators": "bool, default false",+   "excludeValues": "bool, default false",+   "useDrillOrigin": "bool, default false"+  },+  "output": {+   "files": "[{layer, path}]"+  },+  "hint": "One file per layer, named after the board and the layer. For an enclosure drawing export Edge.Cuts with contours:true.",+  "pitfalls": [+   "The board's DXF only: a mechanical DXF of a 3D design is a different job and not this verb."+  ],+  "related": [+   "render_board_layers",+   "export_step"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "layers": [+    "Edge.Cuts"+   ],+   "contours": true+  },+  "longRunning": true,+  "timeoutSeconds": 300,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "render_board_3d",+  "tier": "native",+  "summary": "Render a 3D picture of the board from one side to an image file, through the tool's own renderer, without opening a window.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "side": "top|bottom|left|right|front|back, default top",+   "width": "int px, default 1600",+   "height": "int px, default 900",+   "quality": "basic|high, default basic (high raytraces and is much slower)",+   "background": "default|transparent|opaque",+   "zoom": "number, default 1.0",+   "perspective": "bool, default false",+   "format": "png|jpg, default png",+   "outputDir": "folder for the output (default beside the board)"+  },+  "output": {+   "image": "path",+   "width": "int",+   "height": "int",+   "side": "string"+  },+  "hint": "One call per side: top and bottom for a review. A flat image of chosen layers is render_board_layers; show_3d_board opens a window instead.",+  "pitfalls": [+   "Parts without a 3D model render as bare pads: check them with bodies first."+  ],+  "related": [+   "render_board_layers",+   "render_schematic",+   "bodies",+   "show_3d_board"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "side": "top"+  },+  "longRunning": true,+  "timeoutSeconds": 600,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "estimate_cost",+  "tier": "checks",+  "summary": "The board's numbers a fab quote needs (size, layers, thickness, smallest track, gap and drill, holes, SMD and through-hole parts and joints, unique parts) and a rough price table at the quantities asked, with every assumption stated and the price source named with the date it was read.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "quantities": "[5, 10, 30, 100] (default)",+   "assembly": "bool, default false: add an assembly estimate",+   "fab": "the price list to use, default jlcpcb"+  },+  "output": {+   "board": "{sizeMm, layers, thicknessMm, minTrackMm, minGapMm, minDrillMm, holes, smdParts, thtParts, smdJoints, thtJoints, uniqueParts}",+   "prices": "[{quantity, board, assembly, total, currency}]",+   "assumptions": "[string]",+   "source": "{name, url, read: date}"+  },+  "hint": "An order of magnitude, not a quote: parts, shipping and options are left out. For a real quote send the manufacturing files to the fab.",+  "pitfalls": [+   "Prices change: source names the price list and the date it was read; an old date means an old price."+  ],+  "related": [+   "fab_check",+   "export_manufacturing",+   "bom"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "quantities": [+    5,+    50+   ]+  },+  "longRunning": false,+  "timeoutSeconds": 60,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "remove_parts",+  "tier": "core",+  "summary": "Remove placed parts from the board by designator, as one undo step. The library is not touched (that is remove_footprint).",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",+   "refs": "[\"R7\", \"R8\"] (required)",+   "allowLocked": "bool, default false",+   "dryRun": "bool, default false: answer the plan and change nothing"+  },+  "output": {+   "removed": "[{ref, nets: [string]}]",+   "failed": "[{ref, error}]",+   "revision": "string: the board's new revision"+  },+  "hint": "Each removed part lists the nets its pads carried. A locked part is refused (part_locked) unless allowLocked:true.",+  "pitfalls": [+   "Tracks and vias that met the pads stay: routing_state shows what is left dangling.",+   "A part still in the schematic comes back at the next update_pcb."+  ],+  "related": [+   "move_parts",+   "routing_state",+   "update_pcb"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "refs": [+    "TP3"+   ],+   "expectedRevision": "<rev>"+  },+  "longRunning": true,+  "timeoutSeconds": 130,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "edit_parts",+  "tier": "core",+  "summary": "Edit placed parts: value, designator, any field (add, change, remove), do-not-populate, exclusion from the BOM or position files, mounting type and the lock. One undo step.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",+   "edits": "[{ref, value?, newRef?, fields?: {name: value | null (remove)}, dnp?: bool, excludeFromBom?: bool, excludeFromPos?: bool, mount?: smd|through_hole|other, locked?: bool}] (required)",+   "dryRun": "bool, default false: answer the plan and change nothing"+  },+  "output": {+   "edited": "[{ref, before, after}]",+   "failed": "[{ref, error}]",+   "revision": "string: the board's new revision"+  },+  "hint": "Fields the tool requires (designator, value) cannot be removed. Read the parts first with component_data.",+  "pitfalls": [+   "Board-side edits of what the schematic owns are lost at the next update_pcb: change the schematic instead (sch_edit).",+   "A designator already taken is refused."+  ],+  "related": [+   "component_data",+   "part_parameters",+   "sch_edit"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "edits": [+    {+     "ref": "R7",+     "value": "4k7",+     "dnp": true+    }+   ],+   "expectedRevision": "<rev>"+  },+  "longRunning": true,+  "timeoutSeconds": 130,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "align_parts",+  "tier": "core",+  "summary": "Line parts up on a common left, right, top, bottom or centre line, or space them evenly, by courtyard box or by anchor point. One undo step, with move_parts' checks.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",+   "refs": "[\"C1\", \"C2\", \"C3\"] (required)",+   "mode": "left|right|top|bottom|centerX|centerY|distributeX|distributeY (required)",+   "by": "courtyard|anchor, default courtyard",+   "to": "mm: the line to align on (default from the group)",+   "gapMm": "number: the spacing for distribute (default even spacing between the outer two)",+   "allowOverlap": "bool, default false",+   "allowOutside": "bool, default false",+   "dryRun": "bool, default false: answer the plan and change nothing"+  },+  "output": {+   "targets": "[{ref, x, y}]",+   "mismatches": "[{ref, asked, got}]",+   "revision": "string: the board's new revision"+  },+  "hint": "Without to, left takes the group's smallest x, right the largest, top the highest edge and bottom the lowest (y up); centre lines take the mean. distribute keeps the outer two in place.",+  "pitfalls": [+   "Rotation and side are kept: align parts of the same orientation for a clean row.",+   "A courtyard collision or a part off the board is refused, as in move_parts."+  ],+  "related": [+   "move_parts",+   "placement_check"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "refs": [+    "C4",+    "C5",+    "C6"+   ],+   "mode": "top",+   "expectedRevision": "<rev>"+  },+  "longRunning": true,+  "timeoutSeconds": 130,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "set_layer_count",+  "tier": "core",+  "summary": "Set the board's copper layer count (2, 4, 6 or 8): the layer table and the stack-up, keeping the board thickness.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "count": "2|4|6|8 (required)",+   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",+   "dryRun": "bool, default false: answer the plan and change nothing"+  },+  "output": {+   "layers": "[string]: the copper layers now",+   "stackup": "the new stack-up, as layer_stack answers it",+   "revision": "string: the board's new revision"+  },+  "hint": "New inner layers are signal layers In1.Cu ... Read the result with layer_stack.",+  "pitfalls": [+   "A layer being removed that still carries copper or graphics is refused (layers_in_use, with the counts per layer).",+   "New dielectrics are generic: re-check an impedance-controlled stack-up with layer_stack.",+   "Net classes and design rules are not changed."+  ],+  "related": [+   "layer_stack",+   "copper_layers",+   "layers_in_use"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "count": 4+  },+  "longRunning": false,+  "timeoutSeconds": 60,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "remove_graphics",+  "tier": "core",+  "summary": "Remove board graphics (lines, rectangles, circles, arcs, polygons, texts, dimensions) by id, or every one on a layer and of a kind. One undo step.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",+   "ids": "[id]",+   "layer": "\"F.SilkS\": every graphic on this layer",+   "kinds": "[line|rect|circle|arc|polygon|text|dimension]",+   "dryRun": "bool, default false: answer the plan and change nothing"+  },+  "output": {+   "removed": "[{id, kind, layer, points}]",+   "revision": "string: the board's new revision"+  },+  "hint": "Board-level graphics only; graphics inside parts are footprint_primitives. An unknown id refuses the whole call (unknown_ids).",+  "pitfalls": [+   "Removing Edge.Cuts graphics removes the board outline.",+   "A layer or kind filter without ids removes every match: dry-run it first."+  ],+  "related": [+   "remove_items",+   "footprint_primitives",+   "silk_state"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "layer": "Dwgs.User",+   "dryRun": true+  },+  "longRunning": true,+  "timeoutSeconds": 130,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "import_svg",+  "tier": "core",+  "summary": "Import SVG artwork (a logo, a label) as filled polygons on a silkscreen, copper, mask or user layer, at a position and size; curves flattened, holes kept. One undo step.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",+   "svgPath": "path to the .svg",+   "svg": "the SVG text (instead of svgPath)",+   "at": "[x, y] mm (required)",+   "widthMm": "number: the artwork's width (or scale)",+   "scale": "number, default 1",+   "anchor": "topleft|center, default topleft: which point of the artwork at names",+   "layer": "default F.SilkS",+   "mirror": "bool, default true on bottom layers",+   "net": "a net for artwork on copper",+   "toleranceMm": "number, default 0.02: curve flattening",+   "dryRun": "bool, default false: answer the plan and change nothing"+  },+  "output": {+   "polygons": "int",+   "sizeMm": "[w, h]",+   "ids": "[id]",+   "skipped": "[{element, why}]",+   "revision": "string: the board's new revision"+  },+  "hint": "Filled shapes import; text and images are listed in skipped (convert text to paths first). A shape inside another becomes a hole.",+  "pitfalls": [+   "Stroke-only artwork imports nothing: give the SVG filled shapes.",+   "On copper the shapes are graphics: give net to tie them to a net, and run run_drc.",+   "On a bottom layer the artwork is mirrored so it reads correctly from the back; mirror:false keeps it as drawn."+  ],+  "related": [+   "apply_silkscreen",+   "silk_state",+   "run_drc"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "svgPath": "C:/proj/logo.svg",+   "at": [+    120,+    95+   ],+   "widthMm": 10,+   "layer": "F.SilkS",+   "expectedRevision": "<rev>"+  },+  "longRunning": true,+  "timeoutSeconds": 130,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "copy_routing",+  "tier": "core",+  "summary": "Copy the tracks and vias inside a box to an offset, remapping nets by pairing parts (a designator map or pattern), so a repeated channel gets the same routing. One undo step.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",+   "box": "[x1, y1, x2, y2] mm (required): the source",+   "offset": "[dx, dy] mm (required)",+   "refMap": "{\"U1\": \"U5\"}: pair parts, so each pad's net maps to the partner pad's net",+   "refPattern": "{from: \"CH1_*\", to: \"CH2_*\"}: pair parts by designator pattern",+   "netMap": "{\"SIG\": \"SIG2\"}: overrides",+   "keepUnmappedNets": "bool, default false",+   "layers": "[layer]: copy only these",+   "validate": "bool, default true: run the tool's DRC on the result before committing",+   "dryRun": "bool, default false: answer the plan and change nothing"+  },+  "output": {+   "copied": "{tracks: int, vias: int}",+   "netMap": "{from: to}: the pairing used",+   "skipped": "[{item, why}]",+   "drc": "{ran, newErrors}",+   "revision": "string: the board's new revision"+  },+  "hint": "A track is copied when both ends are in the box, a via when its centre is. Without a remap the copy keeps its nets. Dry-run first and check netMap.",+  "pitfalls": [+   "Only through vias are copied: blind and buried vias are skipped.",+   "The copy connects only where the target pads sit at the same offset: place the target channel identically first (replicate_layout).",+   "One source net mapping to two target nets is refused (net_map_conflict) unless netMap settles it."+  ],+  "related": [+   "replicate_layout",+   "route_net",+   "routing_state"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "box": [+    10,+    10,+    30,+    25+   ],+   "offset": [+    25,+    0+   ],+   "refPattern": {+    "from": "CH1_*",+    "to": "CH2_*"+   },+   "expectedRevision": "<rev>"+  },+  "longRunning": true,+  "timeoutSeconds": 130,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "cross_probe",+  "tier": "app",+  "summary": "From a schematic part to the board part linked to it, and back, by designator, the schematic symbol's id or its sheet path; optionally select them in the tool.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "ref": "\"U1\"",+   "symbolId": "the schematic symbol's id",+   "path": "the symbol's sheet path",+   "schematic": "path to a sheet of the project (default the project's)",+   "select": "bool, default false: also select the matches in the tool"+  },+  "output": {+   "matches": "[{board: {ref, id, side, x, y, rotation}, schematic: {sheet, id, ref, symbol, value}, linked: bool}]",+   "symbolWithoutPart": "[ref]"+  },+  "hint": "Reads the open board when the tool serves it, else the file.",+  "pitfalls": [+   "linked:false means the board part has no link to a symbol: placed by hand, or update_pcb never ran."+  ],+  "related": [+   "selection",+   "update_pcb",+   "component_data"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "ref": "U3"+  },+  "longRunning": false,+  "timeoutSeconds": 60,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "check_clearance",+  "tier": "checks",+  "summary": "Measure the gaps between parts, courtyard to courtyard or pad copper to pad copper, for the listed parts or the whole board, and report every pair under a threshold, closest first.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "refs": "[\"U1\", \"C3\"]: keep pairs that involve one of these (default every part)",+   "mode": "courtyard|pads, default courtyard",+   "thresholdMm": "number, default 0.25 (courtyard) or 0.2 (pads)",+   "includeSameNet": "bool, default false (pads)",+   "maxPairs": "int, default 200"+  },+  "output": {+   "pairs": "[{a, b, distanceMm, overlapping: bool, touching: bool}]",+   "clean": "bool",+   "thresholdMm": "number",+   "measuredOn": "courtyard outline|courtyard box|pads"+  },+  "hint": "Computed from the board model: courtyards compare only parts on the same side, pads only copper that shares a side.",+  "pitfalls": [+   "Rounded pads may be measured as their full rectangle, so a gap can read a little small: the tool's DRC (run_drc) is the authority."+  ],+  "related": [+   "placement_check",+   "run_drc",+   "align_parts"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "refs": [+    "U1"+   ],+   "mode": "pads",+   "thresholdMm": 0.2+  },+  "longRunning": false,+  "timeoutSeconds": 60,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "place_decoupling",+  "tier": "checks",+  "summary": "Plan positions for decoupling capacitors beside an IC's power pins (each cap just outside the courtyard, its power pad facing the pin), answered as move_parts arguments; dryRun:false applies them through move_parts.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "ic": "\"U1\" (required)",+   "caps": "[\"C1\", \"C2\"] (default every capacitor across ground and one of the IC's power nets)",+   "gapMm": "number, default 0.3",+   "dryRun": "bool, default TRUE",+   "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed (to apply)"+  },+  "output": {+   "placements": "[{cap, pin, side, x, y, rotation, padToPinMm}]",+   "skipped": "[{cap, why: other_side|no_shared_power_net|no_free_spot}]",+   "moveArgs": "move_parts arguments",+   "validation": "move_parts' courtyard and outline check of the plan",+   "revision": "string, when applied"+  },+  "hint": "Read the plan, then apply it with dryRun:false and expectedRevision, or send moveArgs to move_parts yourself.",+  "pitfalls": [+   "Caps on the other side of the board are skipped: move them to the IC's side first (move_parts with side).",+   "It places; it does not route: route the stubs with route_net."+  ],+  "related": [+   "move_parts",+   "route_net",+   "placement_check"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "ic": "U1"+  },+  "longRunning": true,+  "timeoutSeconds": 130,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "plan_fanout",+  "tier": "checks",+  "summary": "Plan the fanout of a BGA or QFN/QFP: the pad pitch, dogbone or via-in-pad per pad, the escape layer, surface stubs for the outer ring and a via grid for an exposed pad, answered as route_net arguments, one call per net.",+  "input": {+   "filePath": "path to the board file (default: the board open in the tool)",+   "ref": "\"U3\" (required)",+   "style": "auto|dogbone|via-in-pad, default auto",+   "escapeLayer": "a layer name (default the first inner layer, else the opposite side)",+   "viaMm": "via diameter",+   "viaDrillMm": "via drill",+   "widthMm": "track width",+   "clearanceMm": "number, default 0.1",+   "pitchMm": "override the detected pitch",+   "stubMm": "number, default 0.4",+   "surfaceOuterRing": "bool, default true"+  },+  "output": {+   "package": "bga|perimeter",+   "pitchMm": "number",+   "style": "string",+   "pads": "[{pad, net, action: surface|dogbone|via-in-pad|stub+via|thermal-via-grid|skip}]",+   "calls": "[route_net arguments]",+   "minViaToPadMm": "number"+  },+  "hint": "auto picks dogbone when a via fits between four pads with the clearance, else via-in-pad. Send each call to route_net with filePath and expectedRevision, dry run first.",+  "pitfalls": [+   "Via-in-pad needs filled and capped vias (IPC-4761 type VII): tell the user before committing it.",+   "The plan does not check stubs against other parts' copper; route_net checks each call before it commits."+  ],+  "related": [+   "route_net",+   "place_vias",+   "fab_check"+  ],+  "example": {+   "filePath": "C:/proj/Board.PcbDoc",+   "ref": "U3"+  },+  "longRunning": false,+  "timeoutSeconds": 60,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "project_create",+  "tier": "core",+  "summary": "Create a new project folder with a project file, an empty schematic and an empty board (2 to 32 copper layers), with a title and text variables.",+  "input": {+   "parentDir": "folder to create the project in (required)",+   "name": "string (required): the project and folder name",+   "title": "string",+   "layers": "int, default 2",+   "fabRules": "a fab name from adom/pcb-design-rules, recorded to apply once the board has content",+   "textVariables": "{\"REV\": \"A\"}",+   "dryRun": "bool, default false: answer the plan and change nothing"+  },+  "output": {+   "project": "path",+   "files": "[path]"+  },+  "hint": "Next: draw the outline (set_outline), then place and route. fabRules is recorded, not applied.",+  "pitfalls": [+   "A folder that already holds a project is refused.",+   "The board has no outline yet: set it before routing or exporting."+  ],+  "related": [+   "project_info",+   "sch_create",+   "set_outline"+  ],+  "example": {+   "parentDir": "C:/Users/me/Documents/Projects",+   "name": "widget",+   "layers": 4+  },+  "longRunning": false,+  "timeoutSeconds": 30,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "project_info",+  "tier": "core",+  "summary": "A project at a glance: name, files with sizes and dates, the sheet tree, the board (layers, parts, nets, size), text variables, net classes, last change, and whether the tool has it open. Read only.",+  "input": {+   "project": "path to the project file, its folder or any of its documents (required)"+  },+  "output": {+   "name": "string",+   "files": "[{path, bytes, modified}]",+   "sheets": "the sheet tree, as sch_hierarchy answers it",+   "board": "{layers, parts, nets, sizeMm}",+   "textVariables": "{name: value}",+   "netClasses": "[string]",+   "modified": "date",+   "open": "bool: the tool has a document of this project open"+  },+  "hint": "Read this before renaming, snapshotting or editing a project.",+  "pitfalls": [],+  "related": [+   "sch_hierarchy",+   "board_summary",+   "open_project"+  ],+  "example": {+   "project": "C:/proj/Board.PrjPcb"+  },+  "longRunning": false,+  "timeoutSeconds": 30,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "project_rename",+  "tier": "core",+  "summary": "Rename a project: the project file, the root sheet, the board and the tool's side files, with the references inside them updated. Refused while the tool has the project open.",+  "input": {+   "project": "path to the project file (required)",+   "newName": "string (required)",+   "dryRun": "bool, default false: answer the plan and change nothing"+  },+  "output": {+   "renamed": "[{from, to}]",+   "changed": "[{file, what}]"+  },+  "hint": "Dry-run first: the plan lists every file renamed and what changes inside each. Close the project in the tool first.",+  "pitfalls": [+   "Child sheet files keep their names; only the documents named after the project are renamed.",+   "The folder keeps its name.",+   "Take a project_snapshot first if the project is not under version control."+  ],+  "related": [+   "project_snapshot",+   "project_info",+   "close"+  ],+  "example": {+   "project": "C:/proj/Old.PrjPcb",+   "newName": "widget-v2",+   "dryRun": true+  },+  "longRunning": false,+  "timeoutSeconds": 60,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "project_snapshot",+  "tier": "native",+  "summary": "A dated copy of the project's documents into <project>/snapshots/<stamp>[-label]/, with PDFs of the schematic and the board made by the tool.",+  "input": {+   "project": "path to the project file (required)",+   "label": "string: added to the folder name",+   "pdfs": "bool, default true"+  },+  "output": {+   "folder": "path",+   "files": "[path]",+   "pdfs": "{made: [path], skipped: why}"+  },+  "hint": "Take one before a risky edit (a rename, a big re-route). Libraries in sub-folders are referenced, not copied.",+  "pitfalls": [+   "A snapshot of an open project holds what is saved on disk, not unsaved edits: save first."+  ],+  "related": [+   "project_rename",+   "export_pdf",+   "save"+  ],+  "example": {+   "project": "C:/proj/Board.PrjPcb",+   "label": "before-routing"+  },+  "longRunning": true,+  "timeoutSeconds": 300,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "read_footprint",+  "tier": "core",+  "summary": "Every detail of one library footprint: pads (number, type, shape, position, size, drill, layers), the layers it uses, its courtyard box, graphics per layer, attributes, properties and 3D models. The library mirror of read_symbol; footprint_primitives reads a part placed on the board.",+  "input": {+   "libraryPath": "path to the footprint library",+   "name": "the footprint's name (with libraryPath)",+   "libId": "\"Lib:Name\": resolved through the project's and then the global library table",+   "project": "path to the project, for libId"+  },+  "output": {+   "name": "string",+   "pads": "[{number, type, shape, at, sizeMm, drillMm, layers, rotation}]",+   "layers": "[string]",+   "courtyardMm": "[x1, y1, x2, y2]",+   "graphics": "{layer: count}",+   "attributes": "{mount, excludeFromBom, excludeFromPos, dnp}",+   "properties": "{name: value}",+   "models": "[{path, offset, scale, rotate}]"+  },+  "hint": "Read before edit_footprint, and to check pin 1 and the pad numbers against the symbol.",+  "pitfalls": [],+  "related": [+   "edit_footprint",+   "read_symbol",+   "footprint_primitives",+   "list_library"+  ],+  "example": {+   "libId": "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm"+  },+  "longRunning": false,+  "timeoutSeconds": 60,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "edit_footprint",+  "tier": "core",+  "summary": "Edit a library footprint in place: change, delete, add or renumber pads; add, replace or delete graphics on a layer; set its description, tags and attributes; replace, add or delete 3D models. Everything not edited stays as it was.",+  "input": {+   "libraryPath": "path to the footprint library (required)",+   "name": "the footprint's name (required)",+   "pads": "[{number, set?: {sizeMm, at, shape, drillMm, layers, rotation, type, newNumber}, delete?: true}]",+   "addPads": "[pad]",+   "renumber": "{map: {\"1\": \"A1\"}} | {sequential: true, start?: 1}",+   "graphics": "[{layer, mode: append|replace|delete, widthMm?, shapes: [{type: line|arc|rect|circle|poly, ...}]}]",+   "metadata": "{description?, tags?, attributes?: {mount, excludeFromBom, excludeFromPos, dnp}}",+   "models": "{mode: replace|append|delete, list: [{path, offset, scale, rotate}]}",+   "dryRun": "bool, default false: answer the plan and change nothing"+  },+  "output": {+   "changes": "[string]: what was done, in order"+  },+  "hint": "Operations run in the order pads, addPads, renumber, graphics, metadata, models. An edited pad keeps its id.",+  "pitfalls": [+   "Boards that already use the footprint keep their own copy: update them with swap_footprint.",+   "Graphics replace and delete touch shapes only, never text on that layer."+  ],+  "related": [+   "read_footprint",+   "create_footprint",+   "swap_footprint",+   "add_body"+  ],+  "example": {+   "libraryPath": "C:/lib/Mine.PcbLib",+   "name": "SOT-23_Mine",+   "pads": [+    {+     "number": "1",+     "set": {+      "sizeMm": [+       1.0,+       0.8+      ]+     }+    }+   ]+  },+  "longRunning": false,+  "timeoutSeconds": 30,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "export_library_part",+  "tier": "native",+  "summary": "Export one library part into its own small library files: a symbol library with only its symbol, a footprint library with only its footprint, and its 3D model file.",+  "input": {+   "part": "the part's symbol name or library id (required)",+   "footprint": "a footprint name (default the symbol's own)",+   "what": "[symbol, footprint, model] (default all three)",+   "outputDir": "folder for the files"+  },+  "output": {+   "exports": "{symbol: path, footprint: path, model: path}",+   "missing": "[what]"+  },+  "hint": "Use it to hand one part to another project or another tool.",+  "pitfalls": [+   "success is false when any piece asked for is missing; exports still carries what was written."+  ],+  "related": [+   "read_symbol",+   "read_footprint",+   "import_part"+  ],+  "example": {+   "part": "IN-S42ATA"+  },+  "longRunning": true,+  "timeoutSeconds": 130,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]+ },+ {+  "name": "create_part_project",+  "tier": "native",+  "summary": "Generate a small real project (schematic and board) around one library part, so the part can be shown and tested in every view: schematic, 2D board and 3D board.",+  "input": {+   "part": "the part's symbol name or library id (required)",+   "footprint": "a footprint name (default the symbol's own)",+   "projectName": "string (default from the part)",+   "outputDir": "folder (default the user's projects folder)",+   "overwrite": "bool, default false: replace a project of that name"+  },+  "output": {+   "project": "path",+   "schematic": "path",+   "board": "path"+  },+  "hint": "The board keeps the footprint's 3D model, so render_board_3d and show_3d_board show the real part. One part by design.",+  "pitfalls": [+   "The part's symbol and footprint must both be in a library the tool can find.",+   "An existing project of that name is refused unless overwrite:true."+  ],+  "related": [+   "export_library_part",+   "render_board_3d",+   "show_3d_board",+   "import_part"+  ],+  "example": {+   "part": "IN-S42ATR"+  },+  "longRunning": true,+  "timeoutSeconds": 130,+  "proposedBy": "kicad-lane",+  "since": "0.3.0",+  "agreedBy": [+   "altium-lane"+  ]  } ]