EDA Bridge Standard: one way for an AI to drive every PCB tool

@@ -1,6 +1,6 @@ # Coverage: every standard verb on each bridge -Altium bridge 0.2.76 (the reference), KiCad bridge 1.0.62, Fusion 360 bridge 1.12.1. 54 verbs came from other bridges' proposals (tools/proposed/); they are marked *proposed*.+Altium bridge 0.2.76 (the reference), KiCad bridge 1.0.63, Fusion 360 bridge 1.12.1. 54 verbs came from other bridges' proposals (tools/proposed/); they are marked *proposed*. `exact` is the same job under the same or an equivalent name; `partial` does part of it or does it differently; blank is missing. Generated by `tools/generate.py` from `verbs/coverage.json`; do not edit by hand. @@ -22,7 +22,7 @@ Read and edit the design. Every bridge provides these: they are how an AI sees a | `add_body` | Put a 3D body on a footprint of a PcbLib: a STEP model, or an extruded box when no step is given. It REPLACES the footprint's existing 3D bodies (a... | `altium_add_body` |  | `fusion_attach_3d_package` (partial) | | `add_models` | Attach one or more PCBLIB footprint models, parameters, comment and description to a SchLib component (Altium's several-footprints-per-symbol mechanism). | `altium_add_models` | `kicad_footprint_models` (partial) |  | | `add_symbol_art` | Draw the chip-outline artwork (the chip-thumbnailer polylines adom-symbol baked into the KiCad symbol) into a SchLib component, fitted to its body... | `altium_add_symbol_art` |  |  |-| `align_parts` *proposed* | Line parts up on a common left, right, top, bottom or centre line, or space them evenly, by courtyard box or by anchor point. One undo step, with... |  | `kicad_align_footprints` |  |+| `align_parts` *proposed* | Line parts up on a common left, right, top, bottom or centre line, or space them evenly, by courtyard box or by anchor point. One undo step, with... |  | `kicad_align_parts` |  | | `apply_silkscreen` | Land a silkscreen plan in one undo step: designators and comments moved, sized and turned (or hidden), free overlay texts and lines added (bottom texts... | `altium_apply_silkscreen` | `kicad_silk_fields_batch / kicad_silk_text_batch / kicad_silk_graphics_batch` | `fusion_apply_silkscreen` | | `board_outline` | Draw the board shape as tracks and arcs on a mechanical layer: the outline a fab house reads from the Gerbers. A board built by script has its shape but... | `altium_board_outline` | `kicad_board_outline` | `fusion_board_outline` | | `board_shape` | Redefine the CURRENT board's outline as a wMm x hMm rectangle at (x0Mm, y0Mm) by rewriting the board outline's segments. | `altium_board_shape` | `kicad_board_outline` | `fusion_board_shape` |@@ -34,11 +34,11 @@ Read and edit the design. Every bridge provides these: they are how an AI sees a | `copper_layers` | Every copper layer Altium can address on the current board (top, mid 1-30, planes 1-16, bottom) with names and visibility. | `altium_copper_layers` | `kicad_copper_layers` | `fusion_copper_layers` | | `copy_footprint` | Duplicate a footprint inside the current PcbLib under a new name (every primitive replicated). | `altium_copy_footprint` |  |  | | `copy_routing` *proposed* | Copy the tracks and vias inside a box to an offset, remapping nets by pairing parts (a designator map or pattern), so a repeated channel gets the same... |  | `kicad_copy_routing` |  |-| `create_footprint` | Create one footprint from a pad list in a PcbLib (the library is created and saved if the path does not exist) and return a proof frame. | `altium_create_footprint` | `kicad_fp_create` |  |-| `create_symbol` | Create one rectangular symbol from a pin list in a SchLib (the library is created and saved if the path does not exist) and return a proof frame. | `altium_create_symbol` | `kicad_sym_create` |  |+| `create_footprint` | Create one footprint from a pad list in a PcbLib (the library is created and saved if the path does not exist) and return a proof frame. | `altium_create_footprint` | `kicad_create_footprint` |  |+| `create_symbol` | Create one rectangular symbol from a pin list in a SchLib (the library is created and saved if the path does not exist) and return a proof frame. | `altium_create_symbol` | `kicad_create_symbol` |  | | `doc_params` | Read or set a sheet's document parameters: the title block (Title, DocumentNumber, Revision, DrawnBy, Author, CompanyName, ...). | `altium_doc_params` |  |  | | `edit_footprint` *proposed* | Edit a library footprint in place: change, delete, add or renumber pads; add, replace or delete graphics on a layer; set its description, tags and... |  | `kicad_fp_edit` |  |-| `edit_parts` *proposed* | Edit placed parts: value, designator, any field (add, change, remove), do-not-populate, exclusion from the BOM or position files, mounting type and the... |  | `kicad_edit_footprint` |  |+| `edit_parts` *proposed* | Edit placed parts: value, designator, any field (add, change, remove), do-not-populate, exclusion from the BOM or position files, mounting type and the... |  | `kicad_edit_parts` |  | | `find_symbol` | Find symbols (or footprints with kind:'footprint') by part of their name across libraries: the given ones, or every installed .SchLib/.PcbLib. | `altium_find_symbol` | `kicad_find_symbol` |  | | `footprint_primitives` | Geometry dump of one PLACED component: its tracks, arcs, pads (with solder and paste mask expansion in um) and texts in mils with layer ids; other primitive... | `altium_footprint_primitives` | `kicad_footprint_graphics` (partial) |  | | `generate_body` *proposed* | Make a part's 3D body from its package family and its datasheet dimensions (chip, SOIC, QFN, QFP, BGA, SOT-23, DFN, MELF, electrolytic can, crystal, pin... |  |  |  |@@ -61,15 +61,15 @@ Read and edit the design. Every bridge provides these: they are how an AI sees a | `project_info` *proposed* | A project at a glance: name, files with sizes and dates, the sheet tree, the board (layers, parts, nets, size), text variables, net classes, last change,... |  | `kicad_project_info` |  | | `project_rename` *proposed* | Rename a project: the project file, the root sheet, the board and the tool's side files, with the references inside them updated. Refused while the tool has... |  | `kicad_project_rename` |  | | `read_board` | ONE round trip: components, nets, layers, copper, rules, occupancy, outline. | `altium_read_board` | `kicad_board_summary` (partial) | `fusion_board_info / fusion_get_design_info` (partial) |-| `read_footprint` *proposed* | Every detail of one library footprint: pads (number, type, shape, position, size, drill, layers), the layers it uses, its courtyard box, graphics per layer,... |  | `kicad_fp_info` |  |+| `read_footprint` *proposed* | Every detail of one library footprint: pads (number, type, shape, position, size, drill, layers), the layers it uses, its courtyard box, graphics per layer,... |  | `kicad_read_footprint` |  | | `read_rules` | Every design rule on the current board, flat, disabled ones included: name, kind ordinal, enabled, priority, both scope expressions, comment, and Altium's... | `altium_read_rules` | `kicad_list_design_rules` | `fusion_read_rules` | | `read_schematic` | Components on the CURRENT schematic sheet (designator, library reference, comment, position, parameters) in one agent round trip. | `altium_read_schematic` | `kicad_sch_components` (partial) | `fusion_schematic` (partial) |-| `read_symbol` | Read a SchLib component back: description, display-mode count, the pins of mode 0 (designator, name, electrical type), every parameter with its hidden flag,... | `altium_read_symbol` | `kicad_sym_info` |  |+| `read_symbol` | Read a SchLib component back: description, display-mode count, the pins of mode 0 (designator, name, electrical type), every parameter with its hidden flag,... | `altium_read_symbol` | `kicad_read_symbol` |  | | `remove_footprint` | Delete one footprint from the current PcbLib. | `altium_remove_footprint` |  |  |-| `remove_graphics` *proposed* | Remove board graphics (lines, rectangles, circles, arcs, polygons, texts, dimensions) by id, or every one on a layer and of a kind. One undo step. |  | `kicad_delete_graphics` |  |+| `remove_graphics` *proposed* | Remove board graphics (lines, rectangles, circles, arcs, polygons, texts, dimensions) by id, or every one on a layer and of a kind. One undo step. |  | `kicad_remove_graphics` |  | | `remove_items` | Delete specific free tracks and vias, given exactly as altium_routing_state returned them. One undo step. | `altium_remove_items` | `kicad_remove_route` (partial) | `fusion_remove_items` |-| `remove_parts` *proposed* | Remove placed parts from the board by designator, as one undo step. The library is not touched (that is remove_footprint). |  | `kicad_delete_footprint` |  |-| `remove_symbol` | Delete one component from the current SchLib. | `altium_remove_symbol` | `kicad_sym_delete` |  |+| `remove_parts` *proposed* | Remove placed parts from the board by designator, as one undo step. The library is not touched (that is remove_footprint). |  | `kicad_remove_parts` |  |+| `remove_symbol` | Delete one component from the current SchLib. | `altium_remove_symbol` | `kicad_remove_symbol` |  | | `rename_footprint` | Rename a footprint in the current PcbLib. | `altium_rename_footprint` |  |  | | `rename_symbol` | Rename a component (LibReference) in the current SchLib. | `altium_rename_symbol` |  |  | | `ripup_nets` | Delete every free track, arc and via on each named net. One undo step. | `altium_ripup_nets` |  | `fusion_ripup_nets` |@@ -119,8 +119,8 @@ Wraps the EDA tool's own feature (its DRC, ERC, Gerbers, pours, Update PCB). Eve  | Verb | What it does | Altium | KiCad | Fusion 360 | |---|---|---|---|---|-| `add_rule` | Add one SCOPED design rule that set_design_rules' board-wide values cannot express: a net's or class's clearance or width, a length limit, a matched-length... | `altium_add_rule` | `kicad_custom_rules` |  |-| `annotate` | Number every '?' designator (R?, C?, U?) across the project's sheets: the lowest free number per prefix, top-left first on each sheet. dryRun shows the plan. | `altium_annotate` | `kicad_sch_annotate` |  |+| `add_rule` | Add one SCOPED design rule that set_design_rules' board-wide values cannot express: a net's or class's clearance or width, a length limit, a matched-length... | `altium_add_rule` | `kicad_add_rule` |  |+| `annotate` | Number every '?' designator (R?, C?, U?) across the project's sheets: the lowest free number per prefix, top-left first on each sheet. dryRun shows the plan. | `altium_annotate` | `kicad_annotate` |  | | `apply_pours` | Add solid polygon pours from outlines and pour them, each with its own connect style (solid joints or thermal spokes), plus pour keepouts (polygon cutouts);... | `altium_apply_pours` | `kicad_add_zone / kicad_apply_zone_plan` | `fusion_change_pours` (partial) | | `autoroute` | Altium's own autorouter (Situs) on the current board: picks a strategy, keeps existing routing locked by default, routes, and answers the unconnected count... | `altium_autoroute` | `kicad_autoroute` | `fusion_autoroute` | | `build_symbol_modes` | Build ONE SchLib component with N display modes (Normal + Alternate 1..N-1) from a symbol_modes spec file on this machine, and return a proof frame. | `altium_build_symbol_modes` |  |  |@@ -143,18 +143,18 @@ Wraps the EDA tool's own feature (its DRC, ERC, Gerbers, pours, Update PCB). Eve | `install_library` | Register a library file in Altium's Installed Libraries (IntegratedLibraryManager.InstallLibrary) so its parts appear in the Components panel. | `altium_install_library` | `kicad_install_library` |  | | `install_library_bundle` | One-click install of a wiki library bundle (zip of .SchLib/.PcbLib): unpack, register, open the library, prove it with a frame. | `altium_install_library_bundle` | `kicad_install_library_bundle` | `fusion_install_library_bundle` | | `list_installed_libraries` | Every library in Altium's Installed Libraries list (read-only). | `altium_list_installed_libraries` |  |  |-| `net_classes` | Net classes on the current board: list them with their nets, or make one (replacing a class of that name) with an optional width and clearance rule scoped... | `altium_net_classes` | `kicad_netclasses` | `fusion_net_classes` |+| `net_classes` | Net classes on the current board: list them with their nets, or make one (replacing a class of that name) with an optional width and clearance rule scoped... | `altium_net_classes` | `kicad_net_classes` | `fusion_net_classes` | | `netlist` | The compiled netlist of a project: every net with its pins (Designator.Pin) across every sheet, the hierarchy resolved; or one net; or compare with the nets... | `altium_netlist` | `kicad_extract_netlist` | `fusion_netlist` | | `panelize` | Step and repeat a board into a manufacturing panel: a new .PcbDoc holding Altium's own embedded board array of the board (rows x cols), with rails, the... | `altium_panelize` |  |  | | `pcb_report` | Numbers instead of pixels: for a PcbLib, every footprint's pads, pad bounding box, primitive census and 3D bodies; for a board, outline, components with... | `altium_pcb_report` | `kicad_errors` (partial) |  | | `pour_state` | Every polygon pour with the copper it actually poured: filled area per pour and per layer, and the pours that poured nothing. | `altium_pour_state` | `kicad_zone_state` | `fusion_pour_state` | | `project_snapshot` *proposed* | A dated copy of the project's documents into <project>/snapshots/<stamp>[-label]/, with PDFs of the schematic and the board made by the tool. |  | `kicad_project_snapshot` |  | | `remove_pours` | Delete polygon pours by net (and layer), or all of them, and the pour keepouts (cutouts) apply_pours made. Tracks and vias are untouched. | `altium_remove_pours` | `kicad_remove_zone` | `fusion_remove_pours` |-| `render_board_3d` *proposed* | Render a 3D picture of the board from one side to an image file, through the tool's own renderer, without opening a window. |  | `kicad_render_board` |  |+| `render_board_3d` *proposed* | Render a 3D picture of the board from one side to an image file, through the tool's own renderer, without opening a window. |  | `kicad_render_board_3d` |  | | `render_board_layers` *proposed* | Render chosen board layers to an image file without opening a window: a preset view (copper, silkscreen, solder mask, paste, outline, drill, assembly or... |  | `kicad_export_svg` (partial) | `fusion_export_board_image` (partial) | | `render_schematic` *proposed* | Render a sheet to an image without opening a window, through the tool's own plotter, and keep visual baselines: baseline set stores the image, baseline... | `altium_show_schematic` (partial) | `kicad_render_schematic` |  | | `replicate_layout` | Copy one channel's placement to matching channels: each target keeps its anchor part where it is and every other part takes the source's offset and rotation... | `altium_replicate_layout` |  |  |-| `repour` | Repour every polygon on the board (Altium's Repour All) and answer the copper after. Runs outside the script engine so scoped rules apply. | `altium_repour` | `kicad_refill_zones` | `fusion_repour` |+| `repour` | Repour every polygon on the board (Altium's Repour All) and answer the copper after. Runs outside the script engine so scoped rules apply. | `altium_repour` | `kicad_repour` | `fusion_repour` | | `routing_drc` | Design-rule violations on the current board WITH locations, plus the unrouted (ratsnest) count, as one clean/not-clean answer. | `altium_routing_drc` | `kicad_routing_validate` (partial) | `fusion_routing_drc` | | `run_drc` | Run the design rule check on a board and read the violation markers back. PCB:DesignRuleCheck opens a MODAL; the bridge clicks 'Run Design Rule Check'... | `altium_run_drc` | `kicad_run_drc` | `fusion_run_drc` | | `run_erc` | Electrical rules check. Same handler as altium_compile: in Altium, compiling the project IS the ERC. | `altium_run_erc` | `kicad_run_erc` | `fusion_run_erc` |@@ -186,7 +186,7 @@ Engineering computed from the board model, not by the tool: one shared engine, s | `cross_check` | Compare one schematic sheet's designators with a board's. Altium holds ONE current document, so the verb activates the board, reads it, then activates the... | `altium_cross_check` | `kicad_analyze_connections` (partial) |  | | `current_capacity` | Will this trace carry the current? For each power net and its current: the narrowest track on every layer it is routed on against the width IPC-2221 needs... | `altium_current_capacity` |  |  | | `estimate_cost` *proposed* | The board's numbers a fab quote needs (size, layers, thickness, smallest track, gap and drill, holes, SMD and through-hole parts and joints, unique parts)... |  | `kicad_estimate_cost` |  |-| `fab_check` | Before ordering: the board's fab-relevant minimums measured from the live board (narrowest track, smallest via drill, diameter and annular ring, smallest... | `altium_fab_check` | `kicad_validate_for_fab` |  |+| `fab_check` | Before ordering: the board's fab-relevant minimums measured from the live board (narrowest track, smallest via drill, diameter and annular ring, smallest... | `altium_fab_check` | `kicad_fab_check` |  | | `find_space` | Free spots on the board for a part near another (clear of every other part on that side, of that side's tracks and vias, and inside the outline), nearest... | `altium_find_space` |  |  | | `footprint_from_land_pattern` | Build a complete footprint from the land pattern a datasheet prints: pads numbered the standard way (chip, dual SOIC/TSSOP/DFN, SOT, quad QFP/QFN, BGA), an... | `altium_footprint_from_land_pattern` |  |  | | `height_check` | Will it fit the enclosure? Each part's height from its 3D bodies (top and bottom side), the parts over a height limit board-wide or under a lid feature in a... | `altium_height_check` |  |  |@@ -203,7 +203,7 @@ Engineering computed from the board model, not by the tool: one shared engine, s | `read_sheet_file` | Read a schematic sheet straight from its .SchDoc file, without Altium (it need not be installed or running): every part with its designator, library... | `altium_read_sheet_file` |  | `fusion_read_sheet_file` | | `return_path` | Where signal tracks lose their reference: for every signal net, the length of track on each layer that runs over no pour or plane copper on either... | `altium_return_path` |  |  | | `review_board` | Design-review checks (14) over one board read; schematic checks with includeSchematic. | `altium_review_board` | `kicad_lint_board` (partial) |  |-| `route_pair` | Route a differential pair as a pair: one centreline from the source pads' midpoint through waypoints to the destination pads' midpoint, each net offset to... | `altium_route_pair` | `kicad_route_diff_pair` |  |+| `route_pair` | Route a differential pair as a pair: one centreline from the source pads' midpoint through waypoints to the destination pads' midpoint, each net offset to... | `altium_route_pair` | `kicad_route_pair` |  | | `schematic_review` | Review the schematic before Update PCB: every placed pin (read from the sheet files, with its electrical type) against Altium's compiled netlist. Errors:... | `altium_schematic_review` | `kicad_sch_check / kicad_design_review / kicad_lint_schematic` (partial) |  | | `silk_designators` | Place every reference designator the way assembly houses want: one size, upright, beside its own part, clear of every pad (JLCPCB: 0.15 mm), every other... | `altium_silk_designators` |  |  | | `test_board` | Place one footprint, or a ';' list, from the open PcbLib on ONE board: a NEW board (wMm x hMm outline) when pcbPath is new or omitted, APPENDED to the... | `altium_test_board` |  |  |

@@ -6,7 +6,7 @@  },  "proposed": 54,  "compared": {-  "kicad": "1.0.62",+  "kicad": "1.0.63",   "fusion360": "1.12.1"  },  "tiers": {@@ -62,7 +62,7 @@    "source": "proposed",    "altium": null,    "kicad": {-    "verb": "kicad_align_footprints",+    "verb": "kicad_align_parts",     "match": "exact"    },    "fusion360": null@@ -245,7 +245,7 @@     "match": "exact"    },    "kicad": {-    "verb": "kicad_fp_create",+    "verb": "kicad_create_footprint",     "match": "exact"    },    "fusion360": null@@ -259,7 +259,7 @@     "match": "exact"    },    "kicad": {-    "verb": "kicad_sym_create",+    "verb": "kicad_create_symbol",     "match": "exact"    },    "fusion360": null@@ -292,7 +292,7 @@    "source": "proposed",    "altium": null,    "kicad": {-    "verb": "kicad_edit_footprint",+    "verb": "kicad_edit_parts",     "match": "exact"    },    "fusion360": null@@ -608,7 +608,7 @@    "source": "proposed",    "altium": null,    "kicad": {-    "verb": "kicad_fp_info",+    "verb": "kicad_read_footprint",     "match": "exact"    },    "fusion360": null@@ -656,7 +656,7 @@     "match": "exact"    },    "kicad": {-    "verb": "kicad_sym_info",+    "verb": "kicad_read_symbol",     "match": "exact"    },    "fusion360": null@@ -678,7 +678,7 @@    "source": "proposed",    "altium": null,    "kicad": {-    "verb": "kicad_delete_graphics",+    "verb": "kicad_remove_graphics",     "match": "exact"    },    "fusion360": null@@ -706,7 +706,7 @@    "source": "proposed",    "altium": null,    "kicad": {-    "verb": "kicad_delete_footprint",+    "verb": "kicad_remove_parts",     "match": "exact"    },    "fusion360": null@@ -720,7 +720,7 @@     "match": "exact"    },    "kicad": {-    "verb": "kicad_sym_delete",+    "verb": "kicad_remove_symbol",     "match": "exact"    },    "fusion360": null@@ -1304,7 +1304,7 @@     "match": "exact"    },    "kicad": {-    "verb": "kicad_custom_rules",+    "verb": "kicad_add_rule",     "match": "exact"    },    "fusion360": null@@ -1318,7 +1318,7 @@     "match": "exact"    },    "kicad": {-    "verb": "kicad_sch_annotate",+    "verb": "kicad_annotate",     "match": "exact"    },    "fusion360": null@@ -1625,7 +1625,7 @@     "match": "exact"    },    "kicad": {-    "verb": "kicad_netclasses",+    "verb": "kicad_net_classes",     "match": "exact"    },    "fusion360": {@@ -1726,7 +1726,7 @@    "source": "proposed",    "altium": null,    "kicad": {-    "verb": "kicad_render_board",+    "verb": "kicad_render_board_3d",     "match": "exact"    },    "fusion360": null@@ -1779,7 +1779,7 @@     "match": "exact"    },    "kicad": {-    "verb": "kicad_refill_zones",+    "verb": "kicad_repour",     "match": "exact"    },    "fusion360": {@@ -2102,7 +2102,7 @@     "match": "exact"    },    "kicad": {-    "verb": "kicad_validate_for_fab",+    "verb": "kicad_fab_check",     "match": "exact"    },    "fusion360": null@@ -2301,7 +2301,7 @@     "match": "exact"    },    "kicad": {-    "verb": "kicad_route_diff_pair",+    "verb": "kicad_route_pair",     "match": "exact"    },    "fusion360": null