EDA Bridge Standard: one way for an AI to drive every PCB tool

@@ -1,924 +0,0 @@-[- {-  "name": "sch_connect_pins",-  "tier": "core",-  "summary": "Wire pins to pins on a sheet by Ref.Pin: an L-shaped route (one horizontal and one vertical leg) for each pair, with a junction dot wherever a route meets an existing wire in a T. One undo step.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "pairs": "[{from: \"U1.1\", to: \"R5.2\", first?: h|v (the leg to draw first; default along the axis the from pin points), via?: [[x, y], ...] mm waypoints}] (required)",-   "dryRun": "bool, default false: answer the plan and change nothing",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "wired": "int",-   "routes": "[{from, to, points: [[x, y]], ids: [wire id]}]",-   "junctionsAdded": "[[x, y]]",-   "failed": "[{from, to, error}]",-   "saved": "bool"-  },-  "hint": "Pins are matched by number, then by name. Aligned pins get one straight wire; otherwise the route turns once. Check the result with sch_pins (connectedPins) or run_erc.",-  "pitfalls": [-   "The route does not avoid part bodies or other wires: a leg running along another wire merges the two nets. Steer with first or via, and check with sch_pins."-  ],-  "related": [-   "sch_pins",-   "sch_connect",-   "sch_delete_wire",-   "run_erc"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "pairs": [-    {-     "from": "U1.1",-     "to": "R2.1"-    },-    {-     "from": "U1.2",-     "to": "C3.1",-     "first": "v"-    }-   ]-  },-  "longRunning": true,-  "timeoutSeconds": 120,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_connect_to_bus",-  "tier": "core",-  "summary": "Fan pins onto a bus: for each pin a wire running to the bus, a 45-degree bus entry onto it and a member label (D0, D1 ...) on the wire. One undo step.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "pins": "[\"U1.1\", \"U1.2\"] Ref.Pin, in member order (required)",-   "bus": "id of the bus segment (default the only bus on the sheet)",-   "members": "[\"D0\", \"D1\"]: the member names in pin order",-   "prefix": "\"D\": or name members prefix + number",-   "start": "int, default 0: the first number with prefix",-   "entry": "up|down (a vertical bus) or left|right (a horizontal bus): the way the entries lean",-   "busLabel": "\"D[0..7]\": also label the bus",-   "dryRun": "bool, default false: answer the plan and change nothing",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "connected": "[{pin, member, wireId, entryId}]",-   "busLabel": "string or null",-   "failed": "[{pin, error}]",-   "saved": "bool"-  },-  "hint": "Members name the nets: members lists them in pin order, or prefix plus start counts up. Refused with entry_off_bus when an entry would miss the bus: extend the bus with sch_bus first.",-  "pitfalls": [-   "Pins should face the bus; a pin facing away gets a wire across its own part.",-   "Two pins at the same height on a vertical bus share an entry point and collide: offset them or lean the entries differently."-  ],-  "related": [-   "sch_bus",-   "sch_bus_entry",-   "sch_pins"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "pins": [-    "U1.1",-    "U1.7"-   ],-   "prefix": "D",-   "busLabel": "D[0..1]"-  },-  "longRunning": true,-  "timeoutSeconds": 120,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_junction",-  "tier": "core",-  "summary": "Add junction dots at points, or remove dots by id or point. One undo step.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "points": "[[x, y], ...] mm: where to add dots",-   "remove": "[id or [x, y], ...]: dots to remove",-   "dryRun": "bool, default false: answer the plan and change nothing",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "added": "[{id, at}]",-   "removed": "[id]",-   "skipped": "[[x, y]]: points that already had a dot",-   "notNeeded": "[[x, y]]: added dots where fewer than three items meet (legal, but they join nothing extra)",-   "saved": "bool"-  },-  "hint": "The wiring verbs add the dots they need on their own; use this for a T made by hand, or to clean up.",-  "pitfalls": [-   "Items join only where their coordinates match exactly: use pin ends from sch_pins, or points on the sheet's grid."-  ],-  "related": [-   "sch_items",-   "sch_split_wire",-   "sch_delete_wire"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "points": [-    [-     110.49,-     60.96-    ]-   ]-  },-  "longRunning": true,-  "timeoutSeconds": 120,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_bus",-  "tier": "core",-  "summary": "Draw a bus as a polyline (one bus segment per pair of points), optionally with a bus label such as D[0..7] or a group {SDA SCL} at its first point. One undo step.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "points": "[[x, y], [x, y], ...] mm (required)",-   "label": "\"D[0..7]\" or \"{SDA SCL}\": the nets the bus carries",-   "dryRun": "bool, default false: answer the plan and change nothing",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "ids": "[bus segment id]",-   "label": "{id, text} or null",-   "saved": "bool"-  },-  "hint": "A bus carries the nets its label names, and each member wire needs its own label. sch_connect_to_bus does the member wires, entries and labels for a set of pins.",-  "pitfalls": [-   "A bus with no label carries nothing: ERC reports its members as unconnected."-  ],-  "related": [-   "sch_bus_entry",-   "sch_connect_to_bus",-   "sch_delete_wire",-   "sch_items"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "points": [-    [-     203.2,-     50.8-    ],-    [-     203.2,-     101.6-    ]-   ],-   "label": "D[0..7]"-  },-  "longRunning": true,-  "timeoutSeconds": 120,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_bus_entry",-  "tier": "core",-  "summary": "Add 45-degree bus entries: the short diagonal that joins a member wire's end to a bus. One undo step.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "entries": "[{at: [x, y] mm (the wire end), direction: up-right|down-right|up-left|down-left as seen (default down-right)}] (required)",-   "dryRun": "bool, default false: answer the plan and change nothing",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "added": "[{id, at, end: [x, y] (the bus side), onBus: bool}]",-   "saved": "bool"-  },-  "hint": "end is the bus side of each entry; onBus says whether it lands on a bus segment.",-  "pitfalls": [-   "The bus side must touch a bus and the other end a wire end, exactly, or ERC reports the entry as unconnected."-  ],-  "related": [-   "sch_bus",-   "sch_connect_to_bus",-   "sch_items"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "entries": [-    {-     "at": [-      200.66,-      63.5-     ],-     "direction": "up-right"-    }-   ]-  },-  "longRunning": true,-  "timeoutSeconds": 120,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_split_wire",-  "tier": "core",-  "summary": "Split the wire through a point into two wires there, with a junction dot at the cut, so a new branch can end on a wire end. One undo step.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "at": "[x, y] mm on the sheet (the tool's sheet origin, y up) (required)",-   "id": "the wire's id, when several wires pass through the point",-   "junction": "bool, default true",-   "dryRun": "bool, default false: answer the plan and change nothing",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "ids": "[first half (keeps the wire's id), second half (new id)]",-   "junction": "{id, at} or null",-   "saved": "bool"-  },-  "hint": "Split a wire where a new branch should join it, then wire to the cut.",-  "pitfalls": [-   "The point must lie on the wire and not at either end (not_on_wire otherwise)."-  ],-  "related": [-   "sch_delete_wire",-   "sch_junction",-   "sch_items"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "at": [-    110.49,-    60.96-   ]-  },-  "longRunning": true,-  "timeoutSeconds": 120,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_delete_wire",-  "tier": "core",-  "summary": "Delete wires or bus segments by id, by their two ends, or every wire through a point, and remove junction dots that no longer join three or more items. One undo step.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "ids": "[wire id, ...]",-   "from": "[x, y] mm, with to: the wire with exactly these ends (either order)",-   "to": "[x, y] mm",-   "at": "[x, y] mm: every wire passing through the point",-   "dryRun": "bool, default false: answer the plan and change nothing",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "deleted": "[{id, from, to}]",-   "junctionsRemoved": "[[x, y]]",-   "saved": "bool"-  },-  "hint": "Read ids with sch_items. from/to matches one segment, not a whole route.",-  "pitfalls": [-   "A polyline drawn in the editor is several wires sharing ends: from/to names one segment of it."-  ],-  "related": [-   "sch_items",-   "sch_split_wire",-   "sch_junction",-   "sch_connect_pins"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "from": [-    100.33,-    60.96-   ],-   "to": [-    120.65,-    60.96-   ]-  },-  "longRunning": true,-  "timeoutSeconds": 120,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_edit_label",-  "tier": "core",-  "summary": "Edit net labels: rotate, move to a point or by a delta, rename, or move every label of a net at once. One undo step.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "edits": "[{id | text (with at?: [x, y] to pick one) | net (every label of the net), rotation?: 0|90|180|270, to?: [x, y] mm (one label only), by?: [dx, dy] mm, rename?: string}] (required)",-   "dryRun": "bool, default false: answer the plan and change nothing",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "edited": "[{id, text, at, rotation}]",-   "failed": "[{edit, error}]",-   "saved": "bool"-  },-  "hint": "text picks every label with that text (or the one at at); net picks every label of the net. Read ids with sch_items.",-  "pitfalls": [-   "A label joins a net only where it sits on a wire or a pin end: moving it off disconnects it.",-   "rename changes only the labels picked: other labels with the old name stay on the old net."-  ],-  "related": [-   "sch_items",-   "sch_connect",-   "sch_edit"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "edits": [-    {-     "net": "VOUT",-     "by": [-      0,-      2.54-     ]-    }-   ]-  },-  "longRunning": true,-  "timeoutSeconds": 120,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_move_region",-  "tier": "core",-  "summary": "Move everything inside a box by (dx, dy): parts, wire ends inside the box (wires crossing its edge stretch), labels, junctions, no-connect markers, texts, bus entries and sheet symbols. One undo step.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "box": "[x1, y1, x2, y2] mm (required)",-   "by": "[dx, dy] mm (required)",-   "wires": "bool, default true: move wires, buses and bus entries",-   "labels": "bool, default true: move labels and texts",-   "junctions": "bool, default true: move junctions and no-connect markers",-   "dryRun": "bool, default false: answer the plan and change nothing",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "moved": "{parts, wires, buses, busEntries, labels, texts, junctions, noConnects, sheets: [id]}",-   "saved": "bool"-  },-  "hint": "Parts move by their anchor point. Move by a pure dx or a pure dy to keep stretched wires straight.",-  "pitfalls": [-   "A wire with one end in the box stretches diagonally when dx and dy are both non-zero.",-   "Keep the move on the sheet's grid, or pins and wires stop meeting.",-   "A multi-part component whose parts sit on both sides of the edge splits up."-  ],-  "related": [-   "sch_edit",-   "sch_items"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "box": [-    90,-    40,-    160,-    120-   ],-   "by": [-    25.4,-    0-   ]-  },-  "longRunning": true,-  "timeoutSeconds": 120,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_text",-  "tier": "core",-  "summary": "Add free text to a sheet (a note, a title, a design comment) with size, angle, justification, bold and italic. Text has no electrical meaning. One undo step.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "texts": "[{text, at: [x, y] mm, rotation?: 0|90|180|270, sizeMm?: 1.27, justify?: \"left bottom\", bold?: false, italic?: false}] (required)",-   "dryRun": "bool, default false: answer the plan and change nothing",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "added": "[{id, text, at}]",-   "saved": "bool"-  },-  "hint": "Net names are labels, not text: use sch_connect for them. Newlines in text become line breaks.",-  "pitfalls": [],-  "related": [-   "sch_items",-   "sch_edit_label"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "texts": [-    {-     "text": "USB input stage",-     "at": [-      50.8,-      30.48-     ],-     "sizeMm": 2.54,-     "bold": true-    }-   ]-  },-  "longRunning": true,-  "timeoutSeconds": 120,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_page",-  "tier": "core",-  "summary": "Read or set a sheet's page: paper size, orientation and title block (title, date, revision, company, comment lines).",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "paper": "A5 to A0, A to E, USLetter, USLegal, USLedger or custom",-   "orientation": "portrait|landscape",-   "widthMm": "number (custom paper)",-   "heightMm": "number (custom paper)",-   "title": "string",-   "date": "string",-   "rev": "string",-   "company": "string",-   "comments": "[string]: comment lines in order",-   "dryRun": "bool, default false: answer the plan and change nothing",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "paper": "string",-   "widthMm": "number",-   "heightMm": "number",-   "orientation": "string",-   "titleBlock": "{title, date, rev, company, comments}",-   "changed": "bool",-   "saved": "bool"-  },-  "hint": "With no change arguments it only reads. An empty string removes a title-block field. Each sheet of a hierarchy has its own page.",-  "pitfalls": [-   "Shrinking the paper moves nothing: items outside the new frame stay where they are (render_schematic shows it)."-  ],-  "related": [-   "sch_create",-   "render_schematic"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "paper": "A3",-   "title": "Main board",-   "rev": "B"-  },-  "longRunning": false,-  "timeoutSeconds": 30,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_items",-  "tier": "core",-  "summary": "List a sheet's wiring items with ids and coordinates: wires, buses, bus entries, net labels (local, global, hierarchical), power ports, junctions, no-connect markers, texts and sheet symbols. Read only.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "kinds": "[wires, buses, busEntries, labels, powerPorts, junctions, noConnects, texts, sheets] (default all)"-  },-  "output": {-   "wires": "[{id, from, to}]",-   "buses": "[{id, from, to}]",-   "busEntries": "[{id, at, end}]",-   "labels": "[{id, text, kind: local|global|hierarchical, at, rotation}]",-   "powerPorts": "[{id, net, at}]",-   "junctions": "[{id, at}]",-   "noConnects": "[{id, at}]",-   "texts": "[{id, text, at}]",-   "sheets": "[{id, name, file, at, sizeMm}]",-   "counts": "{kind: int}"-  },-  "hint": "The ids feed sch_delete_wire, sch_edit_label, sch_junction and sch_edit. Parts are in schematic_data.",-  "pitfalls": [-   "A wire is one straight segment: a polyline drawn in the editor is several wires sharing ends."-  ],-  "related": [-   "schematic_data",-   "sch_pins",-   "sch_delete_wire",-   "sch_edit_label"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "kinds": [-    "wires",-    "labels"-   ]-  },-  "longRunning": false,-  "timeoutSeconds": 30,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_pins",-  "tier": "core",-  "summary": "Every pin of the named parts on a sheet: its absolute position (rotation and mirror applied), number, name, electrical type, the side it leaves the body, and the wires, labels and nets touching it. Read only.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "references": "[\"U1\", \"R5\"] (default every part)",-   "connections": "bool, default true: add what touches each pin"-  },-  "output": {-   "pins": "[{ref, number, name, type, at: [x, y], direction: right|left|up|down as seen, hidden, touching: [{kind, id}], nets: [string], connectedPins: [Ref.Pin]}]"-  },-  "hint": "at is where a wire or label must land on the pin. connectedPins lists the other pins on the same copper on this sheet.",-  "pitfalls": [-   "Nets here come from this sheet's wires and labels only: netlist gives the project-wide nets.",-   "Hidden power pins (hidden:true) connect by name, not by wire."-  ],-  "related": [-   "sch_connect_pins",-   "sch_connect",-   "schematic_data",-   "netlist"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "references": [-    "U1",-    "R5"-   ]-  },-  "longRunning": false,-  "timeoutSeconds": 30,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_trace_point",-  "tier": "core",-  "summary": "Everything electrically connected at a point on a sheet: the wires, labels, pins, junctions, sheet pins and no-connect markers there, and for each net they belong to the whole net with its name. Read only.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "at": "[x, y] mm on the sheet (the tool's sheet origin, y up) (required)",-   "toleranceMm": "number, default 0.05"-  },-  "output": {-   "items": "[{kind, id, at}]",-   "nets": "[{name, pins: [Ref.Pin], labels, powerPorts, wires, leavesSheet: bool}]",-   "crossingWithoutJunction": "bool: two wires cross here without connecting",-   "nearest": "[x, y]: the nearest connectable point, when nothing is within tolerance"-  },-  "hint": "Read with the tool's own rules: wire ends join wires and wire middles (a T), labels and junction dots join a wire anywhere along it, pins join wire ends.",-  "pitfalls": [-   "One sheet only: a net that leaves through a global, hierarchical or power label (leavesSheet:true) continues on other sheets. netlist gives the compiled net."-  ],-  "related": [-   "sch_pins",-   "net_connections",-   "netlist"-  ],-  "example": {-   "sheet": "C:/proj/Power.SchDoc",-   "at": [-    109.22,-    73.66-   ]-  },-  "longRunning": false,-  "timeoutSeconds": 30,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_hierarchy",-  "tier": "core",-  "summary": "The sheet tree of a design, recursively: each sheet's name, file, id, instance path, page number, position, size and pins. renumber:true renumbers pages depth-first from the root.",-  "input": {-   "sheet": "path to the root sheet",-   "project": "path to the project (instead of sheet)",-   "renumber": "bool, default false",-   "dryRun": "bool, default false: answer the plan and change nothing"-  },-  "output": {-   "tree": "[{name, file, id, path, page, at, sizeMm, pins: [{name, kind}], children: [...]}]",-   "problems": "[{sheet, problem: missing|unreadable|recursive}]",-   "duplicatePages": "[int]",-   "renumbered": "[{sheet, from, to}]"-  },-  "hint": "Pass the root sheet or the project. renumber writes only the numbers that change.",-  "pitfalls": [-   "A sheet file used by two sheet symbols appears twice in the tree (one instance each) but is one file."-  ],-  "related": [-   "sch_sheet_pins",-   "sch_sheet_symbol",-   "sch_create"-  ],-  "example": {-   "project": "C:/proj/Board.PrjPcb",-   "renumber": true-  },-  "longRunning": false,-  "timeoutSeconds": 30,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_sheet_pins",-  "tier": "core",-  "summary": "A sheet symbol's pins: list, add, edit (rename, kind, move along an edge) or delete. import:true adds a pin for every hierarchical port inside the child sheet that the symbol lacks; validate:true reports ports without pins, pins without ports and kind mismatches.",-  "input": {-   "sheet": "path to the parent sheet (required)",-   "sheetSymbol": "the sheet symbol's name or id (default: validate checks every one)",-   "action": "list|add|edit|delete, default list",-   "name": "string: the pin",-   "kind": "input|output|bidirectional|tri_state|passive",-   "side": "left|right|top|bottom",-   "at": "[x, y] mm: snapped to the nearest edge point",-   "newName": "string (edit)",-   "import": "bool",-   "validate": "bool",-   "dryRun": "bool, default false: answer the plan and change nothing",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "pins": "[{id, name, kind, side, at}]",-   "added": "[name]",-   "problems": "[{sheetSymbol, pin, problem: no_port|no_pin|kind_mismatch}]",-   "saved": "bool"-  },-  "hint": "Inputs go on the left edge and outputs on the right by default, in the first free slot. A pin joins the child's hierarchical port of the same name; wire it on the parent side at its at.",-  "pitfalls": [-   "Renaming a pin does not rename the port inside the child sheet: validate afterwards.",-   "A pin moved or deleted leaves its parent-side wire dangling."-  ],-  "related": [-   "sch_sheet_symbol",-   "sch_hierarchy",-   "sch_connect"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "sheetSymbol": "Power",-   "import": true-  },-  "longRunning": false,-  "timeoutSeconds": 30,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_reset_fields",-  "tier": "core",-  "summary": "Put parts' designator and value text (or the named fields) back where the library symbol places them, through each part's rotation and mirror. One undo step.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "references": "[\"R5\", \"C3\"]",-   "all": "bool: every part on the sheet",-   "fields": "[designator, value] by default; other field names as the tool names them",-   "dryRun": "bool, default false: answer the plan and change nothing",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "reset": "[{ref, field}]",-   "saved": "bool"-  },-  "hint": "Font and visibility stay as they are; only position, angle and justification move.",-  "pitfalls": [-   "The library's offsets are what the symbol's author drew; the tool's automatic field placement may put them elsewhere."-  ],-  "related": [-   "sch_edit",-   "schematic_data"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "references": [-    "R5",-    "C3"-   ]-  },-  "longRunning": true,-  "timeoutSeconds": 120,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_update_from_library",-  "tier": "native",-  "summary": "Update the placed symbols on a sheet from their libraries (all, or the listed ones) and report which changed, which already matched and which no library has.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "symbols": "[library symbol name or id, ...] (default all)",-   "library": "path to one library to take them all from (with symbols)",-   "force": "bool, default false: update even when a placed pin would be dropped",-   "dryRun": "bool, default false: answer the plan and change nothing",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "changed": "[{symbol, pinsAdded, pinsRemoved}]",-   "unchanged": "[symbol]",-   "notFound": "[symbol]",-   "refused": "[{symbol, droppedPins}]",-   "saved": "bool"-  },-  "hint": "Run with dryRun first. A symbol whose new version drops a placed pin is refused unless force:true. Check the sheet afterwards with run_erc.",-  "pitfalls": [-   "A pin that moved in the library moves off its wire: check with sch_pins or run_erc after an update that reports changes."-  ],-  "related": [-   "sch_swap_part",-   "schematic_data",-   "run_erc"-  ],-  "example": {-   "sheet": "C:/proj/Main.SchDoc",-   "dryRun": true-  },-  "longRunning": true,-  "timeoutSeconds": 180,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_fix_connectivity",-  "tier": "core",-  "summary": "Snap near-miss wire ends onto the pin, label, sheet pin or wire end they almost touch, within a tolerance. dryRun (the default) lists the moves; dryRun:false makes them.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "toleranceMm": "number, default 0.5",-   "dryRun": "bool, default TRUE",-   "save": "bool, default true: save the sheet after the edit"-  },-  "output": {-   "moves": "[{wireId, from, to, onto: {kind, id}, diagonal: bool}]",-   "unresolved": "[[x, y]]: dangling ends with nothing close",-   "saved": "bool"-  },-  "hint": "Only dangling wire ends move. Read the moves before applying them: diagonal:true means the snapped wire is no longer horizontal or vertical. Check with run_erc after.",-  "pitfalls": [-   "dryRun defaults to true: nothing changes until dryRun:false.",-   "A wide tolerance can snap onto the wrong pin: keep it under half the sheet's grid."-  ],-  "related": [-   "sch_trace_point",-   "run_erc"-  ],-  "example": {-   "sheet": "C:/proj/Power.SchDoc",-   "toleranceMm": 0.5,-   "dryRun": false-  },-  "longRunning": false,-  "timeoutSeconds": 60,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "render_schematic",-  "tier": "native",-  "summary": "Render a sheet to an image without opening a window, through the tool's own plotter, and keep visual baselines: baseline set stores the image, baseline compare reports the pixel drift, the changed region and a diff image.",-  "input": {-   "sheet": "path to the schematic sheet file (required)",-   "width": "int px, default 2000",-   "outputDir": "folder for the image (default beside the project)",-   "baseline": "set|compare",-   "threshold": "percent of pixels, default 0.5 (compare)",-   "drawingSheet": "bool, default true: include the frame and title block"-  },-  "output": {-   "png": "path",-   "width": "int",-   "height": "int",-   "driftPercent": "number (compare)",-   "pass": "bool (compare)",-   "changedRegionMm": "[x1, y1, x2, y2] (compare)",-   "diffPng": "path: the changed pixels in red (compare)",-   "rendererChanged": "bool: the tool's plotter changed since the baseline"-  },-  "hint": "A sub-sheet renders with its real designators. compare renders at the baseline's width and passes when driftPercent <= threshold. show_* verbs open a window; this one does not.",-  "pitfalls": [-   "Anti-aliasing differs between tool versions: rendererChanged:true means drift may not be a design change.",-   "A baseline is per sheet and per width; a paper size change reads as 100 percent drift."-  ],-  "related": [-   "sch_page",-   "export_pdf"-  ],-  "example": {-   "sheet": "C:/proj/Power.SchDoc",-   "baseline": "compare"-  },-  "longRunning": true,-  "timeoutSeconds": 300,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- },- {-  "name": "sch_create",-  "tier": "core",-  "summary": "Create an empty schematic sheet with a paper size and title block; optionally add it to a project as a child sheet of the root. It places no parts or nets (build_schematic does).",-  "input": {-   "sheet": "path of the sheet to create (required)",-   "paper": "A4, A3 ... USLetter or custom",-   "orientation": "portrait|landscape",-   "widthMm": "number (custom)",-   "heightMm": "number (custom)",-   "title": "string",-   "date": "string",-   "rev": "string",-   "company": "string",-   "comments": "[string]",-   "project": "path: add the sheet to this project under its root sheet",-   "sheetName": "string: the sheet symbol's name in the root",-   "at": "[x, y] mm: where the sheet symbol goes on the root",-   "dryRun": "bool, default false: answer the plan and change nothing"-  },-  "output": {-   "sheet": "path",-   "page": "int",-   "sheetSymbol": "{id, name, at} or null",-   "created": "bool"-  },-  "hint": "Without project the sheet stands alone. With project it is linked from the root sheet as a child sheet with the next page number.",-  "pitfalls": [-   "Never overwrites: an existing file is refused.",-   "A new child sheet has no pins on its symbol: add hierarchical ports inside, then sch_sheet_pins {import:true}."-  ],-  "related": [-   "sch_page",-   "sch_hierarchy",-   "sch_sheet_pins",-   "sch_place_part"-  ],-  "example": {-   "sheet": "C:/proj/Power.SchDoc",-   "project": "C:/proj/Board.PrjPcb",-   "sheetName": "Power",-   "title": "Power"-  },-  "longRunning": false,-  "timeoutSeconds": 30,-  "proposedBy": "kicad-lane",-  "since": "0.2.0",-  "agreedBy": [-   "altium-lane"-  ]- }-]