EDA Bridge Standard: one way for an AI to drive every PCB tool

@@ -58,11 +58,11 @@ verb by verb: [docs/coverage.md](docs/coverage.md). | Tier | Verbs | Altium | KiCad | Fusion 360 | |---|---|---|---|---| | **core** | 93 | 86 | 89 | 48 |-| **native** | 46 | 36 | 35 | 19 |+| **native** | 46 | 38 | 39 | 19 | | **checks** | 37 | 33 | 11 | 4 | | **app** | 60 | 56 | 25 | 35 | | **platform** | 19 | 19 | 0 | 0 |-| standard (all but platform) | 236 | 211 | 160 | 106 |+| standard (all but platform) | 236 | 213 | 164 | 106 | <!-- coverage:end -->  The **checks** tier is where the other bridges are furthest behind, and it is the cheapest to close: those verbs are

@@ -1,17 +1,17 @@ # Coverage: every standard verb on each bridge -Altium bridge 0.2.76 (the reference), KiCad bridge 1.0.64, Fusion 360 bridge 1.12.3. 54 verbs came from other bridges' proposals (tools/proposed/); they are marked *proposed*.+Altium bridge 0.2.76 (the reference), KiCad bridge 1.0.65, Fusion 360 bridge 1.12.3. 54 verbs came from other bridges' proposals (tools/proposed/); they are marked *proposed*. `exact` is the same job under the same or an equivalent name; `partial` does part of it or does it differently (`verbs/coverage.json` names what in `note`); `unsupported` answers `not_supported` for the whole job and is not counted; blank is missing. Generated by `tools/generate.py` from `verbs/coverage.json`; do not edit by hand.  | Tier | Verbs | Altium | KiCad | Fusion 360 | |---|---|---|---|---| | **core** | 93 | 86 | 89 | 48 |-| **native** | 46 | 36 | 35 | 19 |+| **native** | 46 | 38 | 39 | 19 | | **checks** | 37 | 33 | 11 | 4 | | **app** | 60 | 56 | 25 | 35 | | **platform** | 19 | 19 | 0 | 0 |-| standard (all but platform) | 236 | 211 | 160 | 106 |+| standard (all but platform) | 236 | 213 | 164 | 106 |  ## core @@ -125,24 +125,24 @@ Wraps the EDA tool's own feature (its DRC, ERC, Gerbers, pours, Update PCB). Eve | `autoroute` | Altium's own autorouter (Situs) on the current board: picks a strategy, keeps existing routing locked by default, routes, and answers the unconnected count... | `altium_autoroute` | `kicad_autoroute` | `fusion_autoroute` | | `build_symbol_modes` | Build ONE SchLib component with N display modes (Normal + Alternate 1..N-1) from a symbol_modes spec file on this machine, and return a proof frame. | `altium_build_symbol_modes` |  |  | | `cleanup_libs` | Remove the factory-default stray every fresh library carries: Component_1 from the current SchLib and an empty (no pads) PCBComponent_1 from the current PcbLib. | `altium_cleanup_libs` |  |  |-| `compile` | Compile a project and return Altium's Messages panel (ERC + connectivity) with counts by class. With no path it compiles Altium's bundled example project. | `altium_compile` |  |  |+| `compile` | Compile a project and return Altium's Messages panel (ERC + connectivity) with counts by class. With no path it compiles Altium's bundled example project. | `altium_compile` | `kicad_compile` |  | | `component_classes` | List, make or remove component classes on the board, each optionally with a room: a placement area that keeps its parts together (fitted around the parts or... | `altium_component_classes` |  |  | | `create_part_project` *proposed* | Generate a small real project (schematic and board) around one library part, so the part can be shown and tested in every view: schematic, 2D board and 3D... |  | `kicad_make_part_project` (partial) |  |-| `diff_pairs` | Differential pairs on the current board: list them, define one from two nets (replacing a pair of that name), or remove one. Altium's differential-pair... | `altium_diff_pairs` |  |  |+| `diff_pairs` | Differential pairs on the current board: list them, define one from two nets (replacing a pair of that name), or remove one. Altium's differential-pair... | `altium_diff_pairs` | `kicad_diff_pairs` |  | | `export_bom` | Bill of materials export: altium_run_outjob with the assembly OutJob and the 'Folder Structure' medium as defaults. | `altium_export_bom` | `kicad_export_bom_csv` (partial) | `fusion_export_bom / fusion_board_bom` | | `export_dxf` *proposed* | Export chosen board layers to DXF, one file per layer (the outline, panel drawings, stencils, enclosure work). |  | `kicad_export_dxf` | `fusion_export_dxf` | | `export_gencad` *proposed* | Export the board as GenCAD 1.4, the input of test-fixture tools and some assembly houses' CAM. |  | `kicad_export_gencad` |  | | `export_gerber` | Gerber/drill export: altium_run_outjob with the fabrication OutJob and the 'Folder Structure' medium as defaults. | `altium_export_gerber` | `kicad_export_gerber` | `fusion_export_gerbers` |-| `export_ipc2581` *proposed* | Export the board as IPC-2581: one XML file with copper, drill, stack-up, netlist and BOM, through the tool's own exporter. |  | `kicad_export_ipc2581` |  |+| `export_ipc2581` *proposed* | Export the board as IPC-2581: one XML file with copper, drill, stack-up, netlist and BOM, through the tool's own exporter. | `altium_export_ipc2581` | `kicad_export_ipc2581` |  | | `export_ipc356` *proposed* | Export the IPC-D-356 netlist of the board, for bare-board electrical test (flying probe or bed of nails). |  | `kicad_export_ipc356` |  | | `export_library_part` *proposed* | Export one library part into its own small library files: a symbol library with only its symbol, a footprint library with only its footprint, and its 3D... |  | `kicad_export_part` (partial) |  | | `export_manufacturing` | A project's manufacturing set in one call: Gerbers, NC drill, pick and place (CSV, mm) and the BOM, from an OutJob the bridge writes beside the project... | `altium_export_manufacturing` | `kicad_export_gerber / kicad_export_pos` (partial) | `fusion_export_gerbers / fusion_export_cpl / fusion_export_bom` (partial) |-| `export_odb` *proposed* | Export the board as ODB++ (copper, drill, stack-up, netlist and parts in one archive) through the tool's own exporter. |  | `kicad_export_odb` |  |+| `export_odb` *proposed* | Export the board as ODB++ (copper, drill, stack-up, netlist and parts in one archive) through the tool's own exporter. | `altium_export_odb` | `kicad_export_odb` |  | | `export_pdf` | Every sheet of a project as one PDF, plus on request the board's composite print, Altium's assembly drawings (top and bottom, designators on the parts) and... | `altium_export_pdf` | `kicad_export_pdf` |  | | `export_step` | Headless STEP export of a board. Default lane 'outjob': Altium's own ExportSTEP output run from a throwaway project in %TEMP% that points at the board - no... | `altium_export_step` | `kicad_export_step` | `fusion_export_step` | | `install_library` | Register a library file in Altium's Installed Libraries (IntegratedLibraryManager.InstallLibrary) so its parts appear in the Components panel. | `altium_install_library` | `kicad_install_library` |  | | `install_library_bundle` | One-click install of a wiki library bundle (zip of .SchLib/.PcbLib): unpack, register, open the library, prove it with a frame. | `altium_install_library_bundle` | `kicad_install_library_bundle` | `fusion_install_library_bundle` |-| `list_installed_libraries` | Every library in Altium's Installed Libraries list (read-only). | `altium_list_installed_libraries` |  |  |+| `list_installed_libraries` | Every library in Altium's Installed Libraries list (read-only). | `altium_list_installed_libraries` | `kicad_list_installed_libraries` |  | | `net_classes` | Net classes on the current board: list them with their nets, or make one (replacing a class of that name) with an optional width and clearance rule scoped... | `altium_net_classes` | `kicad_net_classes` | `fusion_net_classes` | | `netlist` | The compiled netlist of a project: every net with its pins (Designator.Pin) across every sheet, the hierarchy resolved; or one net; or compare with the nets... | `altium_netlist` | `kicad_extract_netlist` | `fusion_netlist` | | `panelize` | Step and repeat a board into a manufacturing panel: a new .PcbDoc holding Altium's own embedded board array of the board (rows x cols), with rails, the... | `altium_panelize` |  |  |@@ -153,7 +153,7 @@ Wraps the EDA tool's own feature (its DRC, ERC, Gerbers, pours, Update PCB). Eve | `render_board_3d` *proposed* | Render a 3D picture of the board from one side to an image file, through the tool's own renderer, without opening a window. |  | `kicad_render_board_3d` |  | | `render_board_layers` *proposed* | Render chosen board layers to an image file without opening a window: a preset view (copper, silkscreen, solder mask, paste, outline, drill, assembly or... |  | `kicad_export_svg` (partial) | `fusion_export_board_image` (partial) | | `render_schematic` *proposed* | Render a sheet to an image without opening a window, through the tool's own plotter, and keep visual baselines: baseline set stores the image, baseline... | `altium_show_schematic` (partial) | `kicad_render_schematic` | `fusion_render_schematic` |-| `replicate_layout` | Copy one channel's placement to matching channels: each target keeps its anchor part where it is and every other part takes the source's offset and rotation... | `altium_replicate_layout` |  |  |+| `replicate_layout` | Copy one channel's placement to matching channels: each target keeps its anchor part where it is and every other part takes the source's offset and rotation... | `altium_replicate_layout` | `kicad_replicate_layout` |  | | `repour` | Repour every polygon on the board (Altium's Repour All) and answer the copper after. Runs outside the script engine so scoped rules apply. | `altium_repour` | `kicad_repour` | `fusion_repour` | | `routing_drc` | Design-rule violations on the current board WITH locations, plus the unrouted (ratsnest) count, as one clean/not-clean answer. | `altium_routing_drc` | `kicad_routing_validate` (partial) | `fusion_routing_drc` | | `run_drc` | Run the design rule check on a board and read the violation markers back. PCB:DesignRuleCheck opens a MODAL; the bridge clicks 'Run Design Rule Check'... | `altium_run_drc` | `kicad_run_drc` | `fusion_run_drc` |

@@ -6,7 +6,7 @@  },  "proposed": 54,  "compared": {-  "kicad": "1.0.64",+  "kicad": "1.0.65",   "fusion360": "1.12.3"  },  "tiers": {@@ -5970,9 +5970,10 @@    "summary": "Before ordering: the board's fab-relevant minimums measured from the live board (narrowest track, smallest via drill, diameter and annular ring, smallest pad hole and ring, smallest SMD pad, clearance rule, copper layers, board size), each with where it is; with a fab's limits, which ones fall short.",    "input": {     "copperOz": "outer copper weight for the preset (default: read from the stack)",-    "fab": "jlcpcb - JLCPCB's published standard capabilities for this board's layer count and copper weight (source and date in the reply)",+    "fab": "a vendor adom/pcb-design-rules covers (jlcpcb, pcbway, osh-park, eurocircuits, aisler, allpcb, elecrow, nextpcb, seeed-fusion, advanced-circuits-4pcb, sierra-circuits, macrofab, adom-3rdpartyfab): its record for this board's layer count (source page and date read in the reply); or a record object from that page",     "filePath": "the .PcbDoc (opened first)",-    "limits": "{minTrack, minClearance, minViaDrill, minViaDiameter, minViaAnnularRing, minPadHole, minPadAnnularRing, minSmdPad, minEdgeClearance, minHoleToHoleVia, minHoleToHolePad, maxDrill, minSilkLine, minSilkText, maxLayers, minBoardMm:[w,h], maxBoardMm:[w,h]} in mm - any fab's numbers; with fab, these override the preset"+    "limits": "{minTrack, minClearance, minViaDrill, minViaDiameter, minViaAnnularRing, minPadHole, minPadAnnularRing, minSmdPad, minEdgeClearance, minHoleToHoleVia, minHoleToHolePad, maxDrill, minSilkLine, minSilkText, maxLayers, minBoardMm:[w,h], maxBoardMm:[w,h]} in mm - any fab's numbers; with fab, these override the preset",+    "process": "the record's process (default standard)"    },    "output": {     "costlierOrBelowRecommended": "[{feature, boardMm, note}]",@@ -5981,7 +5982,7 @@     "measured": "{track, viaDrill, viaDiameter, viaAnnularRing, padHole, padAnnularRing, smdPad, edgeClearance, holeToHoleVia, holeToHolePad, largestDrill, silkText, silkLine: {mm, at}, clearanceRule, copperLayers, boardSize, counts}",     "outsideLimits": "[{limit, limitMm, boardMm, at}]"    },-   "hint": "Look up the fab's own limits (its capability page) and pass them: the bridge does not carry fab numbers, they change. The measured values are what a fab's order form asks for.",+   "hint": "Computed by the EDA Bridge Standard's shared engine (adom-eda-checks). Fab limits come from adom/pcb-design-rules' records, bundled with the bridge: each finding names the vendor's page and the date it was read. limits adds or overrides any limit. The measured values are what a fab's order form asks for.",    "pitfalls": [     "Measures the board as it is now, from the live document: routed copper, vias and pads.",     "Board size is the outline's bounding box."