EDA Bridge Standard: one way for an AI to drive every PCB tool

@@ -1,17 +1,17 @@ # Coverage: every standard verb on each bridge -Altium bridge 0.2.78 (the reference), KiCad bridge 1.0.68, Fusion 360 bridge 1.13.0. 54 verbs came from other bridges' proposals (tools/proposed/); they are marked *proposed*.+Altium bridge 0.2.78 (the reference), KiCad bridge 1.0.68, Fusion 360 bridge 1.13.1. 54 verbs came from other bridges' proposals (tools/proposed/); they are marked *proposed*. `exact` is the same job under the same or an equivalent name; `partial` does part of it or does it differently (`verbs/coverage.json` names what in `note`); `unsupported` answers `not_supported` for the whole job and is not counted; blank is missing. Generated by `tools/generate.py` from `verbs/coverage.json`; do not edit by hand.  | Tier | Verbs | Altium | KiCad | Fusion 360 | |---|---|---|---|---|-| **core** | 93 | 93 | 89 | 73 |-| **native** | 46 | 46 | 41 | 27 |-| **checks** | 37 | 33 | 29 | 9 |+| **core** | 93 | 93 | 89 | 79 |+| **native** | 46 | 46 | 41 | 29 |+| **checks** | 37 | 33 | 29 | 13 | | **app** | 60 | 60 | 25 | 37 | | **platform** | 19 | 19 | 0 | 0 |-| standard (all but platform) | 236 | 232 | 184 | 146 |+| standard (all but platform) | 236 | 232 | 184 | 158 |  ## core @@ -36,11 +36,11 @@ Read and edit the design. Every bridge provides these: they are how an AI sees a | `copy_routing` *proposed* | Copy the tracks and vias inside a box to an offset, remapping nets by pairing parts (a designator map or pattern), so a repeated channel gets the same... | `altium_copy_routing` | `kicad_copy_routing` | `fusion_copy_routing` | | `create_footprint` | Create one footprint from a pad list in a PcbLib (the library is created and saved if the path does not exist) and return a proof frame. | `altium_create_footprint` | `kicad_create_footprint` | `fusion_create_footprint` | | `create_symbol` | Create one rectangular symbol from a pin list in a SchLib (the library is created and saved if the path does not exist) and return a proof frame. | `altium_create_symbol` | `kicad_create_symbol` | `fusion_create_symbol` |-| `doc_params` | Read or set a sheet's document parameters: the title block (Title, DocumentNumber, Revision, DrawnBy, Author, CompanyName, ...). | `altium_doc_params` | `kicad_doc_params` (partial) |  |+| `doc_params` | Read or set a sheet's document parameters: the title block (Title, DocumentNumber, Revision, DrawnBy, Author, CompanyName, ...). | `altium_doc_params` | `kicad_doc_params` (partial) | `fusion_doc_params` (partial) | | `edit_footprint` *proposed* | Edit a library footprint in place: change, delete, add or renumber pads; add, replace or delete graphics on a layer; set its description, tags and... | `altium_edit_footprint` | `kicad_fp_edit` | `fusion_edit_footprint` (partial) | | `edit_parts` *proposed* | Edit placed parts: value, designator, any field (add, change, remove), do-not-populate, exclusion from the BOM or position files, mounting type and the... | `altium_edit_parts` | `kicad_edit_parts` | `fusion_edit_parts` (partial) | | `find_symbol` | Find symbols (or footprints with kind:'footprint') by part of their name across libraries: the given ones, or every installed .SchLib/.PcbLib. | `altium_find_symbol` | `kicad_find_symbol` | `fusion_find_symbol` (partial) |-| `footprint_primitives` | Geometry dump of one PLACED component: its tracks, arcs, pads (with solder and paste mask expansion in um) and texts in mils with layer ids; other primitive... | `altium_footprint_primitives` | `kicad_footprint_graphics` (partial) |  |+| `footprint_primitives` | Geometry dump of one PLACED component: its tracks, arcs, pads (with solder and paste mask expansion in um) and texts in mils with layer ids; other primitive... | `altium_footprint_primitives` | `kicad_footprint_graphics` (partial) | `fusion_footprint_primitives` | | `generate_body` *proposed* | Make a part's 3D body from its package family and its datasheet dimensions (chip, SOIC, QFN, QFP, BGA, SOT-23, DFN, MELF, electrolytic can, crystal, pin... | `altium_generate_body` |  | `fusion_generate_body` | | `import_svg` *proposed* | Import SVG artwork (a logo, a label) as filled polygons on a silkscreen, copper, mask or user layer, at a position and size; curves flattened, holes kept.... | `altium_import_svg` | `kicad_import_svg` | `fusion_import_svg` (partial) | | `layer_stack` | The CURRENT board's stack-up: copper layers in order with copper thickness and the dielectric under each (height, constant, material), and the total... | `altium_layer_stack` | `kicad_layer_stack` | `fusion_board_stackup` |@@ -52,7 +52,7 @@ Read and edit the design. Every bridge provides these: they are how an AI sees a | `move_parts` | Move, rotate and flip placed components (side top or bottom; flip:true turns a part over); each part is read back to 0.001 mm, the exact rotation and its... | `altium_move_parts` | `kicad_move_footprint / kicad_flip_footprint` | `fusion_move_parts` | | `net_connections` | Every pad on the board with its net and owner (Designator.Pad), plus a bounding span and the airline length (minimum spanning tree over its pads, airlineMm)... | `altium_net_connections` | `kicad_trace_net / kicad_find_connections` (partial) | `fusion_net_connections` | | `normalize_bodies` | Move every 3D body of a PcbLib's footprints (or one footprint) onto its pad cluster. A body added through the canvas lands 50000 mil from the pads in the... | `altium_normalize_bodies` |  |  |-| `part_parameters` | The parameter names a project's parts carry (with how many parts carry each), or with name, that parameter's value on every part. | `altium_part_parameters` | `kicad_part_parameters` |  |+| `part_parameters` | The parameter names a project's parts carry (with how many parts carry each), or with name, that parameter's value on every part. | `altium_part_parameters` | `kicad_part_parameters` | `fusion_part_parameters` | | `place_on_pcb` | Place ONE footprint from a PcbLib on a new board and return a proof frame. The single-part predecessor of altium_test_board. | `altium_place_on_pcb` | `kicad_place_footprint / kicad_add_footprint` |  | | `place_on_sch` | Place one symbol, or a ';' list of symbols, from the open SchLib on ONE new sheet (sheet sized FROM the measured parts: 500 mil gaps, 600 mil margins, A4... | `altium_place_on_sch` | `kicad_place_on_sch` |  | | `place_vias` | Place vias (through, top to bottom). One undo step, read back. | `altium_place_vias` | `kicad_add_via` | `fusion_place_vias` |@@ -83,7 +83,7 @@ Read and edit the design. Every bridge provides these: they are how an AI sees a | `sch_connect_to_bus` *proposed* | Fan pins onto a bus: for each pin a wire running to the bus, a 45-degree bus entry onto it and a member label (D0, D1 ...) on the wire. One undo step. | `altium_sch_connect_to_bus` | `kicad_sch_connect_to_bus` | `fusion_sch_connect_to_bus` | | `sch_create` *proposed* | Create an empty schematic sheet with a paper size and title block; optionally add it to a project as a child sheet of the root. It places no parts or nets... | `altium_sch_sheet_symbol` (partial) | `kicad_sch_create` | `fusion_sch_create` (partial) | | `sch_delete_wire` *proposed* | Delete wires or bus segments by id, by their two ends, or every wire through a point, and remove junction dots that no longer join three or more items. One... | `altium_sch_delete_wire` | `kicad_sch_delete_wire` | `fusion_sch_delete_wire` |-| `sch_edit` | Change placed parts on a sheet: move (to x,y mil), moveBy (dx,dy), rotate (degrees), rename (designator), re-comment (comment), delete. One undo step. | `altium_sch_edit` | `kicad_sch_set_property / kicad_sch_move / kicad_sch_delete / kicad_sch_rotate` (partial) |  |+| `sch_edit` | Change placed parts on a sheet: move (to x,y mil), moveBy (dx,dy), rotate (degrees), rename (designator), re-comment (comment), delete. One undo step. | `altium_sch_edit` | `kicad_sch_set_property / kicad_sch_move / kicad_sch_delete / kicad_sch_rotate` (partial) | `fusion_sch_edit` | | `sch_edit_label` *proposed* | Edit net labels: rotate, move to a point or by a delta, rename, or move every label of a net at once. One undo step. | `altium_sch_edit_label` | `kicad_sch_edit_label` | `fusion_sch_edit_label` | | `sch_fix_connectivity` *proposed* | Snap near-miss wire ends onto the pin, label, sheet pin or wire end they almost touch, within a tolerance. dryRun (the default) lists the moves;... | `altium_sch_fix_connectivity` | `kicad_sch_fix_connectivity` | `fusion_sch_fix_connectivity` | | `sch_hierarchy` *proposed* | The sheet tree of a design, recursively: each sheet's name, file, id, instance path, page number, position, size and pins. renumber:true renumbers pages... | `altium_sch_hierarchy` | `kicad_sch_hierarchy` | `fusion_sch_hierarchy` (partial) |@@ -100,14 +100,14 @@ Read and edit the design. Every bridge provides these: they are how an AI sees a | `sch_swap_part` | Replace a placed part with another library part (a different value, package or symbol) at the same place, designator and rotation, keeping its connections:... | `altium_sch_swap_part` | `kicad_sch_replace_symbol` (partial) |  | | `sch_text` *proposed* | Add free text to a sheet (a note, a title, a design comment) with size, angle, justification, bold and italic. Text has no electrical meaning. One undo step. | `altium_sch_text` | `kicad_sch_text` | `fusion_sch_text` | | `sch_trace_point` *proposed* | Everything electrically connected at a point on a sheet: the wires, labels, pins, junctions, sheet pins and no-connect markers there, and for each net they... | `altium_sch_trace_point` | `kicad_sch_trace_point` | `fusion_sch_trace_point` |-| `schematic_data` | Components on a schematic sheet (filePath, else the CURRENT sheet) with their pins (number, name, electrical type), position and orientation. designator... | `altium_schematic_data` | `kicad_sch_components` (partial) |  |+| `schematic_data` | Components on a schematic sheet (filePath, else the CURRENT sheet) with their pins (number, name, electrical type), position and orientation. designator... | `altium_schematic_data` | `kicad_sch_components` (partial) | `fusion_schematic_data` (partial) | | `set_layer_count` *proposed* | Set the board's copper layer count (2, 4, 6 or 8): the layer table and the stack-up, keeping the board thickness. | `altium_set_layer_count` | `kicad_set_layer_count` | `fusion_set_layer_count` | | `set_models` | Replace every footprint model on a SchLib component with ONE PCBLIB model (set_params footprint and add_models APPEND, which is how a symbol ends up with two). | `altium_set_models` | `kicad_footprint_models` (partial) |  | | `set_outline` | Reshape the current board's outline (a rectangle with rounded corners, or a polygon). One undo step. | `altium_set_outline` | `kicad_board_outline` | `fusion_set_outline` | | `set_params` | Set parameters on a SchLib component, optionally its comment, and optionally link a footprint by name. | `altium_set_params` | `kicad_set_params` | `fusion_set_params` (partial) | | `set_track_width` | Set the width of the EXISTING tracks and arcs on nets or a net class (rules only steer new routing). Widen power nets after routing, or thin a net that... | `altium_set_track_width` | `kicad_modify_track` (partial) | `fusion_set_track_width` | | `set_visibility` | Show or hide one named parameter on a SchLib component. | `altium_set_visibility` | `kicad_set_visibility` |  |-| `sheet_params` | Write parameters onto PLACED parts on the schematic sheets (the BOM write-back): MPN, Manufacturer, Mouser/DigiKey/LCSC numbers, anything. A missing... | `altium_sheet_params` | `kicad_sheet_params` |  |+| `sheet_params` | Write parameters onto PLACED parts on the schematic sheets (the BOM write-back): MPN, Manufacturer, Mouser/DigiKey/LCSC numbers, anything. A missing... | `altium_sheet_params` | `kicad_sheet_params` | `fusion_sheet_params` | | `silk_state` | The silkscreen as it stands: every part's body box, its designator and comment (text, location, size, rotation, shown, Altium's measured box), and the free... | `altium_silk_state` | `kicad_silk_state` | `fusion_silk_state` | | `swap_footprint` | Replace the FIRST component on the current board with a footprint from a PcbLib at the same position, re-assigning nets by pad designator. Tracks are... | `altium_swap_footprint` | `kicad_update_footprints_from_library` (partial) |  | | `symbol_prims` | Read a SchLib component's drawing: primitive counts by kind, body rectangle, polyline bounding box, display mode and the footprint models. Read-only, use it... | `altium_symbol_prims` | `kicad_symbol_prims` |  |@@ -120,7 +120,7 @@ Wraps the EDA tool's own feature (its DRC, ERC, Gerbers, pours, Update PCB). Eve | Verb | What it does | Altium | KiCad | Fusion 360 | |---|---|---|---|---| | `add_rule` | Add one SCOPED design rule that set_design_rules' board-wide values cannot express: a net's or class's clearance or width, a length limit, a matched-length... | `altium_add_rule` | `kicad_add_rule` |  |-| `annotate` | Number every '?' designator (R?, C?, U?) across the project's sheets: the lowest free number per prefix, top-left first on each sheet. dryRun shows the plan. | `altium_annotate` | `kicad_annotate` |  |+| `annotate` | Number every '?' designator (R?, C?, U?) across the project's sheets: the lowest free number per prefix, top-left first on each sheet. dryRun shows the plan. | `altium_annotate` | `kicad_annotate` | `fusion_annotate` | | `apply_pours` | Add solid polygon pours from outlines and pour them, each with its own connect style (solid joints or thermal spokes), plus pour keepouts (polygon cutouts);... | `altium_apply_pours` | `kicad_add_zone / kicad_apply_zone_plan` | `fusion_change_pours` (partial) | | `autoroute` | Altium's own autorouter (Situs) on the current board: picks a strategy, keeps existing routing locked by default, routes, and answers the unconnected count... | `altium_autoroute` | `kicad_autoroute` | `fusion_autoroute` | | `build_symbol_modes` | Build ONE SchLib component with N display modes (Normal + Alternate 1..N-1) from a symbol_modes spec file on this machine, and return a proof frame. | `altium_build_symbol_modes` |  |  |@@ -138,7 +138,7 @@ Wraps the EDA tool's own feature (its DRC, ERC, Gerbers, pours, Update PCB). Eve | `export_library_part` *proposed* | Export one library part into its own small library files: a symbol library with only its symbol, a footprint library with only its footprint, and its 3D... | `altium_export_library_part` | `kicad_export_part` (partial) | `fusion_export_library_part` (partial) | | `export_manufacturing` | A project's manufacturing set in one call: Gerbers, NC drill, pick and place (CSV, mm) and the BOM, from an OutJob the bridge writes beside the project... | `altium_export_manufacturing` | `kicad_export_gerber / kicad_export_pos` (partial) | `fusion_export_gerbers / fusion_export_cpl / fusion_export_bom` (partial) | | `export_odb` *proposed* | Export the board as ODB++ (copper, drill, stack-up, netlist and parts in one archive) through the tool's own exporter. | `altium_export_odb` | `kicad_export_odb` | `fusion_export_odb` |-| `export_pdf` | Every sheet of a project as one PDF, plus on request the board's composite print, Altium's assembly drawings (top and bottom, designators on the parts) and... | `altium_export_pdf` | `kicad_export_pdf` |  |+| `export_pdf` | Every sheet of a project as one PDF, plus on request the board's composite print, Altium's assembly drawings (top and bottom, designators on the parts) and... | `altium_export_pdf` | `kicad_export_pdf` | `fusion_export_pdf` (partial) | | `export_step` | Headless STEP export of a board. Default lane 'outjob': Altium's own ExportSTEP output run from a throwaway project in %TEMP% that points at the board - no... | `altium_export_step` | `kicad_export_step` | `fusion_export_step` | | `install_library` | Register a library file in Altium's Installed Libraries (IntegratedLibraryManager.InstallLibrary) so its parts appear in the Components panel. | `altium_install_library` | `kicad_install_library` |  | | `install_library_bundle` | One-click install of a wiki library bundle (zip of .SchLib/.PcbLib): unpack, register, open the library, prove it with a frame. | `altium_install_library_bundle` | `kicad_install_library_bundle` | `fusion_install_library_bundle` |@@ -174,7 +174,7 @@ Engineering computed from the board model, not by the tool: one shared engine, s |---|---|---|---|---| | `assembly_check` | Ready for JLCPCB assembly? The board against both JLCPCB PCBA tiers as published (Economic and Standard): board or panel size, thickness and layers, parts... | `altium_assembly_check` | `kicad_assembly_check` |  | | `auto_classes` | Net classes from the nets' own names: GND, Power (VCC, VDD, 3V3, VBAT...), Clock, HighSpeed (USB, Ethernet, HDMI, PCIe, DDR, MIPI, LVDS, SATA...) and the... | `altium_auto_classes` | `kicad_auto_classes` |  |-| `board_features` | Add the furniture every real board needs in one undo step: mounting holes (at points or the four corners), fiducials, keepout areas, and a stitching-via... | `altium_board_features` | `kicad_add_mounting_hole` (partial) |  |+| `board_features` | Add the furniture every real board needs in one undo step: mounting holes (at points or the four corners), fiducials, keepout areas, and a stitching-via... | `altium_board_features` | `kicad_add_mounting_hole` (partial) | `fusion_board_features` (partial) | | `board_report` | One shareable page per board: every check run against the live board and its project (Altium's DRC, JLCPCB fab limits and assembly tiers, the schematic... | `altium_board_report` | `kicad_board_report` |  | | `bom` | The project's bill of materials read straight from Altium: every schematic sheet the .PrjPcb lists (placed parts and their parameters) merged with the board... | `altium_bom` | `kicad_bom` | `fusion_board_bom` (partial) | | `build_board` | Build a NEW board from a parts list and a netlist: outline (rounded corners allowed), every footprint from one PcbLib placed by its own origin, pad nets... | `altium_build_board` |  |  |@@ -183,7 +183,7 @@ Engineering computed from the board model, not by the tool: one shared engine, s | `check_clearance` *proposed* | Measure the gaps between parts, courtyard to courtyard or pad copper to pad copper, for the listed parts or the whole board, and report every pair under a... | `altium_check_clearance` | `kicad_check_clearance` |  | | `check_orientation` | Advisory: 2-pad parts whose rotation could be better. Each orthogonal rotation is scored in place by airline length (a routable net's MST with the pad... | `altium_check_orientation` | `kicad_check_orientation` |  | | `copper_balance` | How much of each copper layer is copper (tracks, pads, vias and what Altium actually poured, inside the outline; a plane counts full), and how far apart... | `altium_copper_balance` | `kicad_copper_balance` | `fusion_copper_balance` |-| `cross_check` | Compare one schematic sheet's designators with a board's. Altium holds ONE current document, so the verb activates the board, reads it, then activates the... | `altium_cross_check` | `kicad_analyze_connections` (partial) |  |+| `cross_check` | Compare one schematic sheet's designators with a board's. Altium holds ONE current document, so the verb activates the board, reads it, then activates the... | `altium_cross_check` | `kicad_analyze_connections` (partial) | `fusion_cross_check` | | `current_capacity` | Will this trace carry the current? For each power net and its current: the narrowest track on every layer it is routed on against the width IPC-2221 needs... | `altium_current_capacity` | `kicad_current_capacity` | `fusion_current_capacity` | | `estimate_cost` *proposed* | The board's numbers a fab quote needs (size, layers, thickness, smallest track, gap and drill, holes, SMD and through-hole parts and joints, unique parts)... |  | `kicad_estimate_cost` |  | | `fab_check` | Before ordering: the board's fab-relevant minimums measured from the live board (narrowest track, smallest via drill, diameter and annular ring, smallest... | `altium_fab_check` | `kicad_fab_check` | `fusion_fab_check` |@@ -207,8 +207,8 @@ Engineering computed from the board model, not by the tool: one shared engine, s | `schematic_review` | Review the schematic before Update PCB: every placed pin (read from the sheet files, with its electrical type) against Altium's compiled netlist. Errors:... | `altium_schematic_review` | `kicad_sch_check / kicad_design_review / kicad_lint_schematic` (partial) |  | | `silk_designators` | Place every reference designator the way assembly houses want: one size, upright, beside its own part, clear of every pad (JLCPCB: 0.15 mm), every other... | `altium_silk_designators` | `kicad_silk_designators` |  | | `test_board` | Place one footprint, or a ';' list, from the open PcbLib on ONE board: a NEW board (wMm x hMm outline) when pcbPath is new or omitted, APPENDED to the... | `altium_test_board` |  |  |-| `thermal_vias` | A thermal via grid in a part's exposed pad (the ground or thermal pad under a QFN, DFN, PowerPAD or regulator): centred, inset from the pad's edge, sized by... | `altium_thermal_vias` | `kicad_thermal_vias` |  |-| `via_fence` | A via fence for EMC: a row of ground vias on both sides of RF or fast nets' tracks, and/or round the board edge, at a pitch from the frequency (lambda/20)... | `altium_via_fence` | `kicad_via_fence` |  |+| `thermal_vias` | A thermal via grid in a part's exposed pad (the ground or thermal pad under a QFN, DFN, PowerPAD or regulator): centred, inset from the pad's edge, sized by... | `altium_thermal_vias` | `kicad_thermal_vias` | `fusion_thermal_vias` |+| `via_fence` | A via fence for EMC: a row of ground vias on both sides of RF or fast nets' tracks, and/or round the board edge, at a pitch from the frequency (lambda/20)... | `altium_via_fence` | `kicad_via_fence` | `fusion_via_fence` |  ## app 

@@ -7,7 +7,7 @@  "proposed": 54,  "compared": {   "kicad": "1.0.68",-  "fusion360": "1.13.0"+  "fusion360": "1.13.1"  },  "tiers": {   "core": "Read and edit the design. Every bridge provides these: they are how an AI sees and changes a board.",@@ -312,7 +312,11 @@     "match": "partial",     "note": "stores only KiCad's title block fields; the rest are listed in notStored"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_doc_params",+    "match": "partial",+    "note": "the schematic's global attributes (Fusion's title-block values); the sheet is the design's schematic, not a file path"+   }   },   {    "name": "edit_footprint",@@ -380,7 +384,10 @@     "verb": "kicad_footprint_graphics",     "match": "partial"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_footprint_primitives",+    "match": "exact"+   }   },   {    "name": "generate_body",@@ -573,7 +580,10 @@     "verb": "kicad_part_parameters",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_part_parameters",+    "match": "exact"+   }   },   {    "name": "place_on_pcb",@@ -1087,7 +1097,10 @@     "verb": "kicad_sch_set_property / kicad_sch_move / kicad_sch_delete / kicad_sch_rotate",     "match": "partial"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_sch_edit",+    "match": "exact"+   }   },   {    "name": "sch_edit_label",@@ -1368,7 +1381,11 @@     "verb": "kicad_sch_components",     "match": "partial"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_schematic_data",+    "match": "partial",+    "note": "no ComponentKind, item or vault GUIDs (EAGLE parts have none); pins carry their pad numbers and gate"+   }   },   {    "name": "set_layer_count",@@ -1479,7 +1496,10 @@     "verb": "kicad_sheet_params",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_sheet_params",+    "match": "exact"+   }   },   {    "name": "silk_state",@@ -1570,7 +1590,10 @@     "verb": "kicad_annotate",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_annotate",+    "match": "exact"+   }   },   {    "name": "apply_pours",@@ -1853,7 +1876,11 @@     "verb": "kicad_export_pdf",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_export_pdf",+    "match": "partial",+    "note": "sheets and the board composite; Fusion has no assembly-drawing or fabrication-print output"+   }   },   {    "name": "export_step",@@ -2305,7 +2332,11 @@     "verb": "kicad_add_mounting_hole",     "match": "partial"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_board_features",+    "match": "partial",+    "note": "a fiducial is a filled copper circle with its mask opening (an EAGLE board places no loose pads); keepouts are Fusion's restrict layers"+   }   },   {    "name": "board_report",@@ -2431,7 +2462,10 @@     "verb": "kicad_analyze_connections",     "match": "partial"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_cross_check",+    "match": "exact"+   }   },   {    "name": "current_capacity",@@ -2759,7 +2793,10 @@     "verb": "kicad_thermal_vias",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_thermal_vias",+    "match": "exact"+   }   },   {    "name": "via_fence",@@ -2773,7 +2810,10 @@     "verb": "kicad_via_fence",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_via_fence",+    "match": "exact"+   }   },   {    "name": "activate_document",