EDA Bridge Standard: one way for an AI to drive every PCB tool

@@ -62,10 +62,10 @@ verb by verb: [docs/coverage.md](docs/coverage.md). |---|---|---|---|---| | **core** | 93 | 93 | 90 | 82 | | **native** | 46 | 46 | 43 | 33 |-| **checks** | 37 | 37 | 35 | 19 |+| **checks** | 37 | 37 | 35 | 21 | | **app** | 62 | 60 | 38 | 39 | | **platform** | 19 | 19 | 0 | 0 |-| standard (all but platform) | 238 | 236 | 206 | 173 |+| standard (all but platform) | 238 | 236 | 206 | 175 | <!-- coverage:end -->  The **checks** tier is where the other bridges are furthest behind, and it is the cheapest to close: those verbs are

@@ -1,6 +1,6 @@ # Coverage: every standard verb on each bridge -Altium bridge 0.2.80 (the reference), KiCad bridge 1.0.79, Fusion 360 bridge 1.13.9. 56 verbs came from other bridges' proposals (tools/proposed/); they are marked *proposed*.+Altium bridge 0.2.80 (the reference), KiCad bridge 1.0.79, Fusion 360 bridge 1.13.10. 56 verbs came from other bridges' proposals (tools/proposed/); they are marked *proposed*. `exact` is the same job under the same or an equivalent name; `partial` does part of it or does it differently (`verbs/coverage.json` names what in `note`); `unsupported` answers `not_supported` for the whole job and is not counted; blank is missing. Generated by `tools/generate.py` from `verbs/coverage.json`; do not edit by hand. @@ -8,10 +8,10 @@ Generated by `tools/generate.py` from `verbs/coverage.json`; do not edit by hand |---|---|---|---|---| | **core** | 93 | 93 | 90 | 82 | | **native** | 46 | 46 | 43 | 33 |-| **checks** | 37 | 37 | 35 | 19 |+| **checks** | 37 | 37 | 35 | 21 | | **app** | 62 | 60 | 38 | 39 | | **platform** | 19 | 19 | 0 | 0 |-| standard (all but platform) | 238 | 236 | 206 | 173 |+| standard (all but platform) | 238 | 236 | 206 | 175 |  ## core @@ -172,7 +172,7 @@ Engineering computed from the board model, not by the tool: one shared engine, s  | Verb | What it does | Altium | KiCad | Fusion 360 | |---|---|---|---|---|-| `assembly_check` | Ready for JLCPCB assembly? The board against both JLCPCB PCBA tiers as published (Economic and Standard): board or panel size, thickness and layers, parts... | `altium_assembly_check` | `kicad_assembly_check` |  |+| `assembly_check` | Ready for JLCPCB assembly? The board against both JLCPCB PCBA tiers as published (Economic and Standard): board or panel size, thickness and layers, parts... | `altium_assembly_check` | `kicad_assembly_check` | `fusion_assembly_check` | | `auto_classes` | Net classes from the nets' own names: GND, Power (VCC, VDD, 3V3, VBAT...), Clock, HighSpeed (USB, Ethernet, HDMI, PCIe, DDR, MIPI, LVDS, SATA...) and the... | `altium_auto_classes` | `kicad_auto_classes` |  | | `board_features` | Add the furniture every real board needs in one undo step: mounting holes (at points or the four corners), fiducials, keepout areas, and a stitching-via... | `altium_board_features` | `kicad_add_mounting_hole` (partial) | `fusion_board_features` (partial) | | `board_report` | One shareable page per board: every check run against the live board and its project (Altium's DRC, JLCPCB fab limits and assembly tiers, the schematic... | `altium_board_report` | `kicad_board_report` |  |@@ -194,7 +194,7 @@ Engineering computed from the board model, not by the tool: one shared engine, s | `import_part` | One call imports a whole part: footprint spec + STEP + symbol modes + models + params + save. | `altium_import_part` |  |  | | `jlcpcb_order` | A JLCPCB order in one call: the board checked against JLCPCB's fab limits, the Gerbers and drill zipped the way JLCPCB's order page takes them, the JLCPCB... | `altium_jlcpcb_order` | `kicad_jlcpcb_order` |  | | `length_tune` | Lengthen a routed net to a target length, or to match another net (a pair's skew, a DDR byte lane): a serpentine in its longest straight track that has room... | `altium_length_tune` | `kicad_length_tune` |  |-| `net_lengths` | Routed length of every net (or the ones named) on the live board, by layer with its vias; the skew inside each differential pair; and the spread of... | `altium_net_lengths` | `kicad_net_lengths` |  |+| `net_lengths` | Routed length of every net (or the ones named) on the live board, by layer with its vias; the skew inside each differential pair; and the spread of... | `altium_net_lengths` | `kicad_net_lengths` | `fusion_net_lengths` | | `pin_pad_check` | Do the footprints fit their symbols? Part by part, the symbol's pin numbers (from the sheet files) against the footprint's pad names (from the board): pins... | `altium_pin_pad_check` | `kicad_pin_pad_check` |  | | `place_decoupling` *proposed* | Plan positions for decoupling capacitors beside an IC's power pins (each cap just outside the courtyard, its power pad facing the pin), answered as... | `altium_place_decoupling` | `kicad_place_decoupling` | `fusion_place_decoupling` | | `placement_check` | Review the placement before routing: parts whose courtyards (pads and body, grown by a margin) overlap on the same side, parts off the board or over its... | `altium_placement_check` | `kicad_placement_check` | `fusion_placement_check` |

@@ -7,7 +7,7 @@  "proposed": 56,  "compared": {   "kicad": "1.0.79",-  "fusion360": "1.13.9"+  "fusion360": "1.13.10"  },  "tiers": {   "core": "Read and edit the design. Every bridge provides these: they are how an AI sees and changes a board.",@@ -2340,7 +2340,10 @@     "verb": "kicad_assembly_check",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_assembly_check",+    "match": "exact"+   }   },   {    "name": "auto_classes",@@ -2676,7 +2679,10 @@     "verb": "kicad_net_lengths",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_net_lengths",+    "match": "exact"+   }   },   {    "name": "pin_pad_check",

@@ -7,7 +7,7 @@  "proposed": 56,  "compared": {   "kicad": "1.0.79",-  "fusion360": "1.13.9"+  "fusion360": "1.13.10"  },  "tiers": {   "core": "Read and edit the design. Every bridge provides these: they are how an AI sees and changes a board.",