EDA Bridge Standard: one way for an AI to drive every PCB tool

@@ -62,10 +62,10 @@ verb by verb: [docs/coverage.md](docs/coverage.md). |---|---|---|---|---| | **core** | 93 | 93 | 90 | 82 | | **native** | 46 | 46 | 43 | 33 |-| **checks** | 37 | 37 | 35 | 32 |+| **checks** | 37 | 37 | 35 | 36 | | **app** | 62 | 62 | 44 | 45 | | **platform** | 19 | 19 | 0 | 0 |-| standard (all but platform) | 238 | 238 | 212 | 192 |+| standard (all but platform) | 238 | 238 | 212 | 196 | <!-- coverage:end -->  The **checks** tier is where the other bridges are furthest behind, and it is the cheapest to close: those verbs are

@@ -1,6 +1,6 @@ # Coverage: every standard verb on each bridge -Altium bridge 0.2.81 (the reference), KiCad bridge 1.0.84, Fusion 360 bridge 1.13.13. 56 verbs came from other bridges' proposals (tools/proposed/); they are marked *proposed*.+Altium bridge 0.2.81 (the reference), KiCad bridge 1.0.84, Fusion 360 bridge 1.13.14. 56 verbs came from other bridges' proposals (tools/proposed/); they are marked *proposed*. `exact` is the same job under the same or an equivalent name; `partial` does part of it or does it differently (`verbs/coverage.json` names what in `note`); `unsupported` answers `not_supported` for the whole job and is not counted; blank is missing. Generated by `tools/generate.py` from `verbs/coverage.json`; do not edit by hand. @@ -8,10 +8,10 @@ Generated by `tools/generate.py` from `verbs/coverage.json`; do not edit by hand |---|---|---|---|---| | **core** | 93 | 93 | 90 | 82 | | **native** | 46 | 46 | 43 | 33 |-| **checks** | 37 | 37 | 35 | 32 |+| **checks** | 37 | 37 | 35 | 36 | | **app** | 62 | 62 | 44 | 45 | | **platform** | 19 | 19 | 0 | 0 |-| standard (all but platform) | 238 | 238 | 212 | 192 |+| standard (all but platform) | 238 | 238 | 212 | 196 |  ## core @@ -177,7 +177,7 @@ Engineering computed from the board model, not by the tool: one shared engine, s | `board_features` | Add the furniture every real board needs in one undo step: mounting holes (at points or the four corners), fiducials, keepout areas, and a stitching-via... | `altium_board_features` | `kicad_add_mounting_hole` (partial) | `fusion_board_features` (partial) | | `board_report` | One shareable page per board: every check run against the live board and its project (Altium's DRC, JLCPCB fab limits and assembly tiers, the schematic... | `altium_board_report` | `kicad_board_report` | `fusion_board_report` | | `bom` | The project's bill of materials read straight from Altium: every schematic sheet the .PrjPcb lists (placed parts and their parameters) merged with the board... | `altium_bom` | `kicad_bom` | `fusion_board_bom` (partial) |-| `build_board` | Build a NEW board from a parts list and a netlist: outline (rounded corners allowed), every footprint from one PcbLib placed by its own origin, pad nets... | `altium_build_board` | `kicad_build_board` |  |+| `build_board` | Build a NEW board from a parts list and a netlist: outline (rounded corners allowed), every footprint from one PcbLib placed by its own origin, pad nets... | `altium_build_board` | `kicad_build_board` | `fusion_build_board` | | `build_footprint` | Build a complete footprint (pads, silkscreen, courtyard, arcs) in a PcbLib from a kicad2altium spec file on this machine, and return a proof frame. | `altium_build_footprint` |  |  | | `build_schematic` | Draw a design's schematic from its netlist with the project library's symbols, inside a new project (.PrjPcb with the board and libraries), compile it, and... | `altium_build_schematic` | `kicad_build_schematic` | `fusion_schematic_plan / fusion_schematic_run` (partial) | | `check_clearance` *proposed* | Measure the gaps between parts, courtyard to courtyard or pad copper to pad copper, for the listed parts or the whole board, and report every pair under a... | `altium_check_clearance` | `kicad_check_clearance` | `fusion_check_clearance` |@@ -188,10 +188,10 @@ Engineering computed from the board model, not by the tool: one shared engine, s | `estimate_cost` *proposed* | The board's numbers a fab quote needs (size, layers, thickness, smallest track, gap and drill, holes, SMD and through-hole parts and joints, unique parts)... | `altium_estimate_cost` | `kicad_estimate_cost` | `fusion_estimate_cost` | | `fab_check` | Before ordering: the board's fab-relevant minimums measured from the live board (narrowest track, smallest via drill, diameter and annular ring, smallest... | `altium_fab_check` | `kicad_fab_check` | `fusion_fab_check` | | `find_space` | Free spots on the board for a part near another (clear of every other part on that side, of that side's tracks and vias, and inside the outline), nearest... | `altium_find_space` | `kicad_find_space` | `fusion_find_space` |-| `footprint_from_land_pattern` | Build a complete footprint from the land pattern a datasheet prints: pads numbered the standard way (chip, dual SOIC/TSSOP/DFN, SOT, quad QFP/QFN, BGA), an... | `altium_footprint_from_land_pattern` | `kicad_footprint_from_land_pattern` |  |+| `footprint_from_land_pattern` | Build a complete footprint from the land pattern a datasheet prints: pads numbered the standard way (chip, dual SOIC/TSSOP/DFN, SOT, quad QFP/QFN, BGA), an... | `altium_footprint_from_land_pattern` | `kicad_footprint_from_land_pattern` | `fusion_footprint_from_land_pattern` (partial) | | `height_check` | Will it fit the enclosure? Each part's height from its 3D bodies (top and bottom side), the parts over a height limit board-wide or under a lid feature in a... | `altium_height_check` | `kicad_height_check` | `fusion_height_check` | | `impedance` | Controlled impedance from the board's own stack-up: the track width each copper layer needs for a single-ended target (50 ohm default) and the width and gap... | `altium_impedance` | `kicad_impedance` | `fusion_impedance` |-| `import_part` | One call imports a whole part: footprint spec + STEP + symbol modes + models + params + save. | `altium_import_part` |  |  |+| `import_part` | One call imports a whole part: footprint spec + STEP + symbol modes + models + params + save. | `altium_import_part` |  | `fusion_import_part` (partial) | | `jlcpcb_order` | A JLCPCB order in one call: the board checked against JLCPCB's fab limits, the Gerbers and drill zipped the way JLCPCB's order page takes them, the JLCPCB... | `altium_jlcpcb_order` | `kicad_jlcpcb_order` | `fusion_jlcpcb_order` | | `length_tune` | Lengthen a routed net to a target length, or to match another net (a pair's skew, a DDR byte lane): a serpentine in its longest straight track that has room... | `altium_length_tune` | `kicad_length_tune` | `fusion_length_tune` | | `net_lengths` | Routed length of every net (or the ones named) on the live board, by layer with its vias; the skew inside each differential pair; and the spread of... | `altium_net_lengths` | `kicad_net_lengths` | `fusion_net_lengths` |@@ -206,7 +206,7 @@ Engineering computed from the board model, not by the tool: one shared engine, s | `route_pair` | Route a differential pair as a pair: one centreline from the source pads' midpoint through waypoints to the destination pads' midpoint, each net offset to... | `altium_route_pair` | `kicad_route_pair` | `fusion_route_pair` | | `schematic_review` | Review the schematic before Update PCB: every placed pin (read from the sheet files, with its electrical type) against Altium's compiled netlist. Errors:... | `altium_schematic_review` | `kicad_sch_check / kicad_design_review / kicad_lint_schematic` (partial) | `fusion_schematic_review` | | `silk_designators` | Place every reference designator the way assembly houses want: one size, upright, beside its own part, clear of every pad (JLCPCB: 0.15 mm), every other... | `altium_silk_designators` | `kicad_silk_designators` | `fusion_silk_designators` |-| `test_board` | Place one footprint, or a ';' list, from the open PcbLib on ONE board: a NEW board (wMm x hMm outline) when pcbPath is new or omitted, APPENDED to the... | `altium_test_board` | `kicad_test_board` |  |+| `test_board` | Place one footprint, or a ';' list, from the open PcbLib on ONE board: a NEW board (wMm x hMm outline) when pcbPath is new or omitted, APPENDED to the... | `altium_test_board` | `kicad_test_board` | `fusion_test_board` | | `thermal_vias` | A thermal via grid in a part's exposed pad (the ground or thermal pad under a QFN, DFN, PowerPAD or regulator): centred, inset from the pad's edge, sized by... | `altium_thermal_vias` | `kicad_thermal_vias` | `fusion_thermal_vias` | | `via_fence` | A via fence for EMC: a row of ground vias on both sides of RF or fast nets' tracks, and/or round the board edge, at a pitch from the frequency (lambda/20)... | `altium_via_fence` | `kicad_via_fence` | `fusion_via_fence` | 

@@ -7,7 +7,7 @@  "proposed": 56,  "compared": {   "kicad": "1.0.84",-  "fusion360": "1.13.13"+  "fusion360": "1.13.14"  },  "tiers": {   "core": "Read and edit the design. Every bridge provides these: they are how an AI sees and changes a board.",@@ -2426,7 +2426,11 @@     "verb": "kicad_build_board",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_build_board",+    "match": "exact",+    "note": "libraryPath is a .lbr and pcbPath an EAGLE .brd, opened as a local design and read back pin by pin from the live board; outline defaults to the parts' box plus 2 mm"+   }   },   {    "name": "build_footprint",@@ -2604,7 +2608,11 @@     "verb": "kicad_footprint_from_land_pattern",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_footprint_from_land_pattern",+    "match": "partial",+    "note": "the engine's layout written into a .lbr (silk tPlace, fab tDocu, courtyard tKeepout); no 3D body is attached (a 3D package is a Fusion cloud item): fusion_generate_body writes the STEP and fusion_attach_3d_package binds it"+   }   },   {    "name": "height_check",@@ -2649,7 +2657,11 @@     "match": "exact"    },    "kicad": null,-   "fusion360": null+   "fusion360": {+    "verb": "fusion_import_part",+    "match": "partial",+    "note": "the footprint and symbol specs Altium's bridge takes, into one .lbr (pcbLib/schLib are one file in Fusion); an EAGLE symbol has one look, so one display mode is drawn (mode, default 0); a repeated pad number becomes N@2 on the same pin; the STEP binds through the component (needs symbolSpec and a signed-in Fusion)"+   }   },   {    "name": "jlcpcb_order",@@ -2901,7 +2913,11 @@     "verb": "kicad_test_board",     "match": "exact"    },-   "fusion360": null+   "fusion360": {+    "verb": "fusion_test_board",+    "match": "exact",+    "note": "libraryPath is a .lbr and pcbPath an EAGLE .brd, opened as a local design; a plain rectangular outline grows (2 mm margin) to hold appended parts (outlineGrown); any other shape stays and names them in outsideOutline"+   }   },   {    "name": "thermal_vias",

@@ -7,7 +7,7 @@  "proposed": 56,  "compared": {   "kicad": "1.0.84",-  "fusion360": "1.13.13"+  "fusion360": "1.13.14"  },  "tiers": {   "core": "Read and edit the design. Every bridge provides these: they are how an AI sees and changes a board.",@@ -8687,10 +8687,12 @@     "schematic": "the design or sheet to simulate (the bridge's own path or id) (required)",     "analysis": "{type: op} | {type: dc, source, start, stop, step} | {type: ac, sweep: dec|oct|lin, points, start, stop} (Hz) | {type: tran, step, stop, start?} (s) | {type: raw, text: \".ac dec 20 10 1meg\"} (a bridge that cannot run raw SPICE refuses it with not_supported); default the analysis the design carries",     "probes": "[{net: \"OUT\"} | {current: \"V1\"}]; default every net (a bridge may cap the count)",+    "sweep": "{parameter, start, stop, step, scale?: \"lin\" | \"dec\" | \"oct\"}: optional; steps a part's value (\"R4\") or a model parameter (\"Q1.BF\"), one run per value; for lin, step is the increment, for dec and oct the points per decade or octave; a bridge may cap the number of runs",+    "temperatures": "{start, stop, step} (\u00b0C): optional; one run per temperature",     "points": "int, default 200: a ceiling on the points returned per signal; decimation keeps the first and last points and every extremum (the run itself is not coarsened)"    },    "output": {-    "signals": "[{signal: \"V(OUT)\", x: [..], y: [..], xUnit: s|Hz|V, yUnit: V|A|dB, phase?: [..] (AC, degrees, unwrapped)}]; an op gives one point per signal",+    "signals": "[{signal: \"V(OUT)\", x: [..], y: [..], xUnit: s|Hz|V, yUnit: V|A|dB, phase?: [..] (AC, degrees, unwrapped)}]; an op gives one point per signal; with sweep or temperatures each run is its own signal, with step saying which run it is (\"R4 = 300\", \"T = 85\"), so a reader groups runs by signal + step",     "missing": "[probe]: probes the run did not have",     "notSimulated": "[ref]: parts the run left out for want of a simulation model, when the sheet is only partly modelled, so a reader knows the result covers only part of the circuit (empty when every part was simulated)",     "available": "[signal name]",@@ -8700,7 +8702,8 @@    "pitfalls": [     "simulation_failed carries the simulator's own message: a part without a model, a node with no DC path to ground, or a bad analysis.",     "points thins the reply, not the run: a long transient with a tiny step still takes its time.",-    "A partly modelled sheet still runs and names the parts it left out in notSimulated; a sheet with no modelled parts refuses with no_model."+    "A partly modelled sheet still runs and names the parts it left out in notSimulated; a sheet with no modelled parts refuses with no_model.",+    "A bridge that cannot sweep refuses sweep or temperatures with not_supported; it never runs once and returns a single trace as if it were the sweep (ngspice has no .step: loop with alter per value)."    ],    "related": [     "export_spice",