EDA Bridge Standard: one way for an AI to drive every PCB tool

@@ -4151,6 +4151,287 @@    "summary": "Render a sheet to an image without opening a window, through the tool's own plotter, and keep visual baselines: baseline set stores the image, baseline compare reports the pixel drift, the changed region and a diff image.",    "timeoutSeconds": 400   },+  {+   "example": {+    "expectedRevision": "<rev>",+    "filePath": "C:/proj/Board.PcbDoc",+    "refs": [+     "TP3"+    ]+   },+   "hint": "Each removed part lists the nets its pads carried. A locked part is refused (part_locked) unless allowLocked:true.",+   "input": {+    "allowLocked": "bool, default false",+    "dryRun": "bool, default false: answer the plan and change nothing",+    "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",+    "filePath": "path to the board file (default: the board open in the tool)",+    "refs": "[\"R7\", \"R8\"] (required)"+   },+   "longRunning": false,+   "name": "altium_remove_parts",+   "output": {+    "failed": "[{ref, error}]",+    "removed": "[{ref, nets: [string]}]",+    "revision": "string: the board's new revision"+   },+   "pitfalls": [+    "Tracks and vias that met the pads stay: routing_state shows what is left dangling.",+    "A part still in the schematic comes back at the next update_pcb.",+    "Altium's lock is the part's Moveable flag."+   ],+   "related": [+    "altium_routing_state",+    "altium_move_parts"+   ],+   "statusVerb": null,+   "summary": "Remove placed parts from the board by designator, as one undo step. The library is not touched (that is remove_footprint).",+   "timeoutSeconds": 300+  },+  {+   "example": {+    "edits": [+     {+      "dnp": true,+      "ref": "R7",+      "value": "4k7"+     }+    ],+    "expectedRevision": "<rev>",+    "filePath": "C:/proj/Board.PcbDoc"+   },+   "hint": "Fields the tool requires (designator, value) cannot be removed. Read the parts first with component_data.",+   "input": {+    "dryRun": "bool, default false: answer the plan and change nothing",+    "edits": "[{ref, value?, newRef?, fields?: {name: value | null (remove)}, dnp?: bool, excludeFromBom?: bool, excludeFromPos?: bool, mount?: smd|through_hole|other, locked?: bool}] (required)",+    "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",+    "filePath": "path to the board file (default: the board open in the tool)"+   },+   "longRunning": false,+   "name": "altium_edit_parts",+   "output": {+    "edited": "[{ref, before, after}]",+    "failed": "[{ref, error}]",+    "revision": "string: the board's new revision"+   },+   "pitfalls": [+    "Board-side edits of what the schematic owns are lost at the next update_pcb: change the schematic instead (sch_edit).",+    "A designator already taken is refused.",+    "On Altium the board edits designator, value (comment), the lock and BOM exclusion (component kind Standard (no BOM)); do-not-populate is a variant (altium_variants), mounting comes from the footprint and parameters from the schematic: those answer not_supported per field."+   ],+   "related": [+    "altium_routing_state",+    "altium_move_parts"+   ],+   "statusVerb": null,+   "summary": "Edit placed parts: value, designator, any field (add, change, remove), do-not-populate, exclusion from the BOM or position files, mounting type and the lock. One undo step.",+   "timeoutSeconds": 300+  },+  {+   "example": {+    "expectedRevision": "<rev>",+    "filePath": "C:/proj/Board.PcbDoc",+    "mode": "top",+    "refs": [+     "C4",+     "C5",+     "C6"+    ]+   },+   "hint": "Without to, left takes the group's smallest x, right the largest, top the highest edge and bottom the lowest (y up); centre lines take the mean. distribute keeps the outer two in place.",+   "input": {+    "allowOutside": "bool, default false",+    "allowOverlap": "bool, default false",+    "by": "courtyard|anchor, default courtyard",+    "dryRun": "bool, default false: answer the plan and change nothing",+    "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",+    "filePath": "path to the board file (default: the board open in the tool)",+    "gapMm": "number: the spacing for distribute (default even spacing between the outer two)",+    "mode": "left|right|top|bottom|centerX|centerY|distributeX|distributeY (required)",+    "refs": "[\"C1\", \"C2\", \"C3\"] (required)",+    "to": "mm: the line to align on (default from the group)"+   },+   "longRunning": false,+   "name": "altium_align_parts",+   "output": {+    "mismatches": "[{ref, asked, got}]",+    "revision": "string: the board's new revision",+    "targets": "[{ref, x, y}]"+   },+   "pitfalls": [+    "Rotation and side are kept: align parts of the same orientation for a clean row.",+    "A courtyard collision or a part off the board is refused, as in move_parts.",+    "Altium courtyards are not read: the part box is its pads' extent."+   ],+   "related": [+    "altium_routing_state",+    "altium_move_parts"+   ],+   "statusVerb": null,+   "summary": "Line parts up on a common left, right, top, bottom or centre line, or space them evenly, by courtyard box or by anchor point. One undo step, with move_parts' checks.",+   "timeoutSeconds": 300+  },+  {+   "example": {+    "count": 4,+    "filePath": "C:/proj/Board.PcbDoc"+   },+   "hint": "New inner layers are signal layers In1.Cu ... Read the result with layer_stack.",+   "input": {+    "count": "2|4|6|8 (required)",+    "dryRun": "bool, default false: answer the plan and change nothing",+    "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",+    "filePath": "path to the board file (default: the board open in the tool)"+   },+   "longRunning": false,+   "name": "altium_set_layer_count",+   "output": {+    "layers": "[string]: the copper layers now",+    "revision": "string: the board's new revision",+    "stackup": "the new stack-up, as layer_stack answers it"+   },+   "pitfalls": [+    "A layer being removed that still carries copper or graphics is refused (layers_in_use, with the counts per layer).",+    "New dielectrics are generic: re-check an impedance-controlled stack-up with layer_stack.",+    "Net classes and design rules are not changed.",+    "Altium adds inner signal layers (Mid-Layers) and removes inner layers from the bottom up; the board thickness is kept by spreading the dielectrics evenly."+   ],+   "related": [+    "altium_routing_state",+    "altium_move_parts"+   ],+   "statusVerb": null,+   "summary": "Set the board's copper layer count (2, 4, 6 or 8): the layer table and the stack-up, keeping the board thickness.",+   "timeoutSeconds": 300+  },+  {+   "example": {+    "box": [+     10,+     10,+     30,+     25+    ],+    "expectedRevision": "<rev>",+    "filePath": "C:/proj/Board.PcbDoc",+    "offset": [+     25,+     0+    ],+    "refPattern": {+     "from": "CH1_*",+     "to": "CH2_*"+    }+   },+   "hint": "A track is copied when both ends are in the box, a via when its centre is. Without a remap the copy keeps its nets. Dry-run first and check netMap.",+   "input": {+    "box": "[x1, y1, x2, y2] mm (required): the source",+    "dryRun": "bool, default false: answer the plan and change nothing",+    "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",+    "filePath": "path to the board file (default: the board open in the tool)",+    "keepUnmappedNets": "bool, default false",+    "layers": "[layer]: copy only these",+    "netMap": "{\"SIG\": \"SIG2\"}: overrides",+    "offset": "[dx, dy] mm (required)",+    "refMap": "{\"U1\": \"U5\"}: pair parts, so each pad's net maps to the partner pad's net",+    "refPattern": "{from: \"CH1_*\", to: \"CH2_*\"}: pair parts by designator pattern",+    "validate": "bool, default true: run the tool's DRC on the result before committing"+   },+   "longRunning": false,+   "name": "altium_copy_routing",+   "output": {+    "copied": "{tracks: int, vias: int}",+    "drc": "{ran, newErrors}",+    "netMap": "{from: to}: the pairing used",+    "revision": "string: the board's new revision",+    "skipped": "[{item, why}]"+   },+   "pitfalls": [+    "Only through vias are copied: blind and buried vias are skipped.",+    "The copy connects only where the target pads sit at the same offset: place the target channel identically first (replicate_layout).",+    "One source net mapping to two target nets is refused (net_map_conflict) unless netMap settles it.",+    "Arcs are listed under skipped, not copied, on Altium yet.",+    "validate runs Altium's batch DRC before and after: a copy that adds errors is taken back out (rolledBack:true)."+   ],+   "related": [+    "altium_routing_state",+    "altium_move_parts"+   ],+   "statusVerb": null,+   "summary": "Copy the tracks and vias inside a box to an offset, remapping nets by pairing parts (a designator map or pattern), so a repeated channel gets the same routing. One undo step.",+   "timeoutSeconds": 300+  },+  {+   "example": {+    "filePath": "C:/proj/Board.PcbDoc",+    "mode": "pads",+    "refs": [+     "U1"+    ],+    "thresholdMm": 0.2+   },+   "hint": "Computed from the board model: courtyards compare only parts on the same side, pads only copper that shares a side.",+   "input": {+    "filePath": "path to the board file (default: the board open in the tool)",+    "includeSameNet": "bool, default false (pads)",+    "maxPairs": "int, default 200",+    "mode": "courtyard|pads, default courtyard",+    "refs": "[\"U1\", \"C3\"]: keep pairs that involve one of these (default every part)",+    "thresholdMm": "number, default 0.25 (courtyard) or 0.2 (pads)"+   },+   "longRunning": false,+   "name": "altium_check_clearance",+   "output": {+    "clean": "bool",+    "measuredOn": "courtyard outline|courtyard box|pads",+    "pairs": "[{a, b, distanceMm, overlapping: bool, touching: bool}]",+    "thresholdMm": "number"+   },+   "pitfalls": [+    "Rounded pads may be measured as their full rectangle, so a gap can read a little small: the tool's DRC (run_drc) is the authority.",+    "Measured on bounding rectangles from the board model: a rotated or rounded pad reads closer than it is."+   ],+   "related": [+    "altium_routing_state",+    "altium_move_parts"+   ],+   "statusVerb": null,+   "summary": "Measure the gaps between parts, courtyard to courtyard or pad copper to pad copper, for the listed parts or the whole board, and report every pair under a threshold, closest first.",+   "timeoutSeconds": 300+  },+  {+   "example": {+    "dryRun": true,+    "filePath": "C:/proj/Board.PcbDoc",+    "layer": "Dwgs.User"+   },+   "hint": "Board-level graphics only; graphics inside parts are footprint_primitives. An unknown id refuses the whole call (unknown_ids).",+   "input": {+    "dryRun": "bool, default false: answer the plan and change nothing",+    "expectedRevision": "string: the revision you last read (routing_state); refused with stale_board if the board changed",+    "filePath": "path to the board file (default: the board open in the tool)",+    "ids": "[id]",+    "kinds": "[line|rect|circle|arc|polygon|text|dimension]",+    "layer": "\"F.SilkS\": every graphic on this layer"+   },+   "longRunning": false,+   "name": "altium_remove_graphics",+   "output": {+    "removed": "[{id, kind, layer, points}]",+    "revision": "string: the board's new revision"+   },+   "pitfalls": [+    "Removing Edge.Cuts graphics removes the board outline.",+    "A layer or kind filter without ids removes every match: dry-run it first.",+    "With no ids, layer or kinds it only lists the board graphics with their ids (Altium items have none: an id is a hash of kind, layer and geometry)."+   ],+   "related": [+    "altium_routing_state",+    "altium_move_parts"+   ],+   "statusVerb": null,+   "summary": "Remove board graphics (lines, rectangles, circles, arcs, polygons, texts, dimensions) by id, or every one on a layer and of a kind. One undo step.",+   "timeoutSeconds": 300+  },   {    "example": {     "connections": [