skill
EDA Bridge Standard: one way for an AI to drive every PCB tool
Public Made by Adomby adom
The standard every Adom EDA bridge follows so one AI can drive Altium, KiCad, Fusion 360 and any future PCB tool the same way: shared verb names in tiers, the board model JSON, reply and refusal conventions, and a coverage table of each bridge against the Altium reference.
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Fusion: bom is fusion_board_bom (partial: one line per MPN with Mouser, DigiKey and LCSC numbers and the JLCPCB form; no variants or board multiplier); Fusion 78 of 182
4 files changed
+13−6
README.md+2−2@@ -44,10 +44,10 @@ verb by verb: [docs/coverage.md](docs/coverage.md). |---|---|---|---|---| | **core** | 60 | 60 | 38 | 26 | | **native** | 34 | 34 | 23 | 16 |-| **checks** | 32 | 32 | 7 | 2 |+| **checks** | 32 | 32 | 7 | 3 | | **app** | 56 | 56 | 24 | 33 | | **platform** | 19 | 19 | 0 | 0 |-| standard (all but platform) | 182 | 182 | 92 | 77 |+| standard (all but platform) | 182 | 182 | 92 | 78 | <!-- coverage:end --> The **checks** tier is where the other bridges are furthest behind, and it is the cheapest to close: those verbs are
docs/coverage.md+3−3@@ -8,10 +8,10 @@ Generated by `tools/generate.py` from `verbs/coverage.json`; do not edit by hand |---|---|---|---|---| | **core** | 60 | 60 | 38 | 26 | | **native** | 34 | 34 | 23 | 16 |-| **checks** | 32 | 32 | 7 | 2 |+| **checks** | 32 | 32 | 7 | 3 | | **app** | 56 | 56 | 24 | 33 | | **platform** | 19 | 19 | 0 | 0 |-| standard (all but platform) | 182 | 182 | 92 | 77 |+| standard (all but platform) | 182 | 182 | 92 | 78 | ## core @@ -131,7 +131,7 @@ Engineering computed from the board model, not by the tool: one shared engine, s | `auto_classes` | Net classes from the nets' own names: GND, Power (VCC, VDD, 3V3, VBAT...), Clock, HighSpeed (USB, Ethernet, HDMI, PCIe, DDR, MIPI, LVDS, SATA...) and the... | | | | `board_features` | Add the furniture every real board needs in one undo step: mounting holes (at points or the four corners), fiducials, keepout areas, and a stitching-via... | `kicad_add_mounting_hole` (partial) | | | `board_report` | One shareable page per board: every check run against the live board and its project (Altium's DRC, JLCPCB fab limits and assembly tiers, the schematic... | | |-| `bom` | The project's bill of materials read straight from Altium: every schematic sheet the .PrjPcb lists (placed parts and their parameters) merged with the board... | | |+| `bom` | The project's bill of materials read straight from Altium: every schematic sheet the .PrjPcb lists (placed parts and their parameters) merged with the board... | | `fusion_board_bom` (partial) | | `build_board` | Build a NEW board from a parts list and a netlist: outline (rounded corners allowed), every footprint from one PcbLib placed by its own origin, pad nets... | | | | `build_footprint` | Build a complete footprint (pads, silkscreen, courtyard, arcs) in a PcbLib from a kicad2altium spec file on this machine, and return a proof frame. | | | | `build_schematic` | Draw a design's schematic from its netlist with the project library's symbols, inside a new project (.PrjPcb with the board and libraries), compile it, and... | | `fusion_schematic_plan / fusion_schematic_run` (partial) |
tools/equivalents.json+4@@ -8,6 +8,10 @@ "board_info", "partial" ],+ "bom": [+ "board_bom",+ "partial"+ ], "build_schematic": [ "schematic_plan + schematic_run", "partial"
verbs/coverage.json+4−1@@ -1018,7 +1018,10 @@ "tier": "checks", "altium": "altium_bom", "kicad": null,- "fusion360": null+ "fusion360": {+ "verb": "fusion_board_bom",+ "match": "partial"+ } }, { "name": "build_board",