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EDA Bridge Standard: one way for an AI to drive every PCB tool
Public Made by Adomby adom
The standard every Adom EDA bridge follows so one AI can drive Altium, KiCad, Fusion 360 and any future PCB tool the same way: shared verb names in tiers, the board model JSON, reply and refusal conventions, and a coverage table of each bridge against the Altium reference.
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regenerate after fusion-lane (reference/fusion360-1.13.3.json, public: engine 0.4.0, height_check and placement_check new): Fusion 160 of 236
4 files changed
+17−11
README.md+2−2@@ -61,10 +61,10 @@ verb by verb: [docs/coverage.md](docs/coverage.md). |---|---|---|---|---| | **core** | 93 | 93 | 89 | 79 | | **native** | 46 | 46 | 43 | 29 |-| **checks** | 37 | 33 | 34 | 13 |+| **checks** | 37 | 33 | 34 | 15 | | **app** | 60 | 60 | 36 | 37 | | **platform** | 19 | 19 | 0 | 0 |-| standard (all but platform) | 236 | 232 | 202 | 158 |+| standard (all but platform) | 236 | 232 | 202 | 160 | <!-- coverage:end --> The **checks** tier is where the other bridges are furthest behind, and it is the cheapest to close: those verbs are
docs/coverage.md+5−5@@ -1,6 +1,6 @@ # Coverage: every standard verb on each bridge -Altium bridge 0.2.78 (the reference), KiCad bridge 1.0.71, Fusion 360 bridge 1.13.2. 54 verbs came from other bridges' proposals (tools/proposed/); they are marked *proposed*.+Altium bridge 0.2.78 (the reference), KiCad bridge 1.0.71, Fusion 360 bridge 1.13.3. 54 verbs came from other bridges' proposals (tools/proposed/); they are marked *proposed*. `exact` is the same job under the same or an equivalent name; `partial` does part of it or does it differently (`verbs/coverage.json` names what in `note`); `unsupported` answers `not_supported` for the whole job and is not counted; blank is missing. Generated by `tools/generate.py` from `verbs/coverage.json`; do not edit by hand. @@ -8,10 +8,10 @@ Generated by `tools/generate.py` from `verbs/coverage.json`; do not edit by hand |---|---|---|---|---| | **core** | 93 | 93 | 89 | 79 | | **native** | 46 | 46 | 43 | 29 |-| **checks** | 37 | 33 | 34 | 13 |+| **checks** | 37 | 33 | 34 | 15 | | **app** | 60 | 60 | 36 | 37 | | **platform** | 19 | 19 | 0 | 0 |-| standard (all but platform) | 236 | 232 | 202 | 158 |+| standard (all but platform) | 236 | 232 | 202 | 160 | ## core @@ -189,7 +189,7 @@ Engineering computed from the board model, not by the tool: one shared engine, s | `fab_check` | Before ordering: the board's fab-relevant minimums measured from the live board (narrowest track, smallest via drill, diameter and annular ring, smallest... | `altium_fab_check` | `kicad_fab_check` | `fusion_fab_check` | | `find_space` | Free spots on the board for a part near another (clear of every other part on that side, of that side's tracks and vias, and inside the outline), nearest... | `altium_find_space` | `kicad_find_space` | | | `footprint_from_land_pattern` | Build a complete footprint from the land pattern a datasheet prints: pads numbered the standard way (chip, dual SOIC/TSSOP/DFN, SOT, quad QFP/QFN, BGA), an... | `altium_footprint_from_land_pattern` | `kicad_footprint_from_land_pattern` | |-| `height_check` | Will it fit the enclosure? Each part's height from its 3D bodies (top and bottom side), the parts over a height limit board-wide or under a lid feature in a... | `altium_height_check` | `kicad_height_check` | |+| `height_check` | Will it fit the enclosure? Each part's height from its 3D bodies (top and bottom side), the parts over a height limit board-wide or under a lid feature in a... | `altium_height_check` | `kicad_height_check` | `fusion_height_check` | | `impedance` | Controlled impedance from the board's own stack-up: the track width each copper layer needs for a single-ended target (50 ohm default) and the width and gap... | `altium_impedance` | `kicad_impedance` | `fusion_impedance` | | `import_part` | One call imports a whole part: footprint spec + STEP + symbol modes + models + params + save. | `altium_import_part` | | | | `jlcpcb_order` | A JLCPCB order in one call: the board checked against JLCPCB's fab limits, the Gerbers and drill zipped the way JLCPCB's order page takes them, the JLCPCB... | `altium_jlcpcb_order` | `kicad_jlcpcb_order` | |@@ -197,7 +197,7 @@ Engineering computed from the board model, not by the tool: one shared engine, s | `net_lengths` | Routed length of every net (or the ones named) on the live board, by layer with its vias; the skew inside each differential pair; and the spread of... | `altium_net_lengths` | `kicad_net_lengths` | | | `pin_pad_check` | Do the footprints fit their symbols? Part by part, the symbol's pin numbers (from the sheet files) against the footprint's pad names (from the board): pins... | `altium_pin_pad_check` | `kicad_pin_pad_check` | | | `place_decoupling` *proposed* | Plan positions for decoupling capacitors beside an IC's power pins (each cap just outside the courtyard, its power pad facing the pin), answered as... | | `kicad_place_decoupling` | |-| `placement_check` | Review the placement before routing: parts whose courtyards (pads and body, grown by a margin) overlap on the same side, parts off the board or over its... | `altium_placement_check` | `kicad_placement_validate / kicad_score_placement` (partial) | |+| `placement_check` | Review the placement before routing: parts whose courtyards (pads and body, grown by a margin) overlap on the same side, parts off the board or over its... | `altium_placement_check` | `kicad_placement_validate / kicad_score_placement` (partial) | `fusion_placement_check` | | `plan_fanout` *proposed* | Plan the fanout of a BGA or QFN/QFP: the pad pitch, dogbone or via-in-pad per pad, the escape layer, surface stubs for the outer ring and a via grid for an... | | `kicad_plan_fanout` | | | `plan_route` *proposed* | Plan a path for one net between two pads without changing the board: a grid search around the existing copper that keeps the clearance rules, on the allowed... | | | `fusion_plan_route` (partial) | | `read_sheet_file` | Read a schematic sheet straight from its .SchDoc file, without Altium (it need not be installed or running): every part with its designator, library... | `altium_read_sheet_file` | `kicad_read_sheet_file` | `fusion_read_sheet_file` |
verbs/coverage.json+9−3@@ -7,7 +7,7 @@ "proposed": 54, "compared": { "kicad": "1.0.71",- "fusion360": "1.13.2"+ "fusion360": "1.13.3" }, "tiers": { "core": "Read and edit the design. Every bridge provides these: they are how an AI sees and changes a board.",@@ -2564,7 +2564,10 @@ "verb": "kicad_height_check", "match": "exact" },- "fusion360": null+ "fusion360": {+ "verb": "fusion_height_check",+ "match": "exact"+ } }, { "name": "impedance",@@ -2673,7 +2676,10 @@ "verb": "kicad_placement_validate / kicad_score_placement", "match": "partial" },- "fusion360": null+ "fusion360": {+ "verb": "fusion_placement_check",+ "match": "exact"+ } }, { "name": "plan_fanout",
verbs/standard.json+1−1@@ -7,7 +7,7 @@ "proposed": 54, "compared": { "kicad": "1.0.71",- "fusion360": "1.13.2"+ "fusion360": "1.13.3" }, "tiers": { "core": "Read and edit the design. Every bridge provides these: they are how an AI sees and changes a board.",