EDA Bridge Standard: one way for an AI to drive every PCB tool

@@ -1986,5 +1986,73 @@   "agreedBy": [    "altium-lane"   ]+ },+ {+  "name": "simulate",+  "tier": "app",+  "summary": "Run a circuit simulation of the design's schematic and return the signals as data: an operating point, a DC sweep, an AC sweep or a transient, with the nets and source currents asked for.",+  "input": {+   "schematic": "the design or sheet to simulate (the bridge's own path or id) (required)",+   "analysis": "{type: op} | {type: dc, source, start, stop, step} | {type: ac, sweep: dec|oct|lin, points, start, stop} (Hz) | {type: tran, step, stop, start?} (s) | {type: raw, text: \".ac dec 20 10 1meg\"} (a bridge that cannot run raw SPICE refuses it with not_supported); default the analysis the design carries",+   "probes": "[{net: \"OUT\"} | {current: \"V1\"}]; default every net (a bridge may cap the count)",+   "points": "int, default 200: a ceiling on the points returned per signal; decimation keeps the first and last points and every extremum (the run itself is not coarsened)"+  },+  "output": {+   "signals": "[{signal: \"V(OUT)\", x: [..], y: [..], xUnit: s|Hz|V, yUnit: V|A|dB, phase?: [..] (AC, degrees, unwrapped)}]; an op gives one point per signal",+   "missing": "[probe]: probes the run did not have",+   "available": "[signal name]",+   "engine": "the simulator and its version, e.g. \"ngspice 46 (KiCad 10.0.7)\""+  },+  "hint": "AC signals are the magnitude in dB with phase in degrees beside it. Every part needs a simulation model: passives work from their values, sources come from the tool's simulation library, ICs need a model file.",+  "pitfalls": [+   "simulation_failed carries the simulator's own message: a part without a model, a node with no DC path to ground, or a bad analysis.",+   "points thins the reply, not the run: a long transient with a tiny step still takes its time."+  ],+  "related": [+   "export_spice",+   "run_erc",+   "sch_place_part"+  ],+  "example": {+   "schematic": "C:/proj/filter.kicad_sch",+   "analysis": {+    "type": "ac",+    "sweep": "dec",+    "points": 20,+    "start": 10,+    "stop": 1000000+   },+   "probes": [+    {+     "net": "OUT"+    }+   ]+  }+ },+ {+  "name": "export_spice",+  "tier": "app",+  "summary": "Write the design's SPICE netlist with the tool's own exporter, and say what it holds.",+  "input": {+   "schematic": "the design or sheet (required)",+   "outputPath": "path for the netlist (default beside the design)"+  },+  "output": {+   "path": "the netlist file",+   "dialect": "ngspice | pspice | ltspice | xspice",+   "elements": "int: parts in the netlist",+   "analyses": "[the analysis lines the design carries]",+   "includes": "[the model files it includes]"+  },+  "hint": "A part without a simulation model is left out or becomes a comment: give it one before simulating.",+  "pitfalls": [+   "Model files are included by the path the part's model field gives: keep them where every machine finds them."+  ],+  "related": [+   "simulate"+  ],+  "example": {+   "schematic": "C:/proj/filter.kicad_sch"+  }  } ]