component
E-L9823013TR
Public Made by Adomby adom
STMicroelectronics Power Distribution Switches, SO-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+60@@ -0,0 +1,60 @@+# E-L9823013TR++**STMicroelectronics** · Power Distribution Switches · SO-24-300mil++E-L9823013TR from STMicroelectronics, in a SO-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OUT7 | output | Low-side driver output 7 with 0.5 A maximum capability and 50 V typical output clamp voltage for inductive load flyback suppression. |+| 2 | OUT6 | output | Low-side driver output 6 with 0.5 A maximum capability and 50 V typical output clamp voltage for inductive load flyback suppression. |+| 3 | SCLK | input | SPI clock input; 160 ns minimum low time; shifts data on falling edge into shift register and changes SO on rising edge. |+| 4 | SI | input | SPI serial data input; 8-bit instruction stream accepted on falling edge of SCLK with MSB first; logic level selects output on/off on CSB rising edge. |+| 5 | GND | power_in | Analog ground connection point. |+| 6 | GND | power_in | Analog ground connection point. |+| 7 | GND | power_in | Analog ground connection point. |+| 8 | GND | power_in | Analog ground connection point. |+| 9 | SO | tri_state | Tri-state SPI serial output reporting drain status; remains high-impedance until CSB goes low; changes state on rising SCLK edge with 100 ns maximum propagation delay. |+| 10 | CSB | input | Active-low chip select input enabling SPI communication; latches output control data on rising edge; must transition only when SCLK is low. |+| 11 | OUT5 | output | Low-side driver output 5 with 0.5 A maximum capability and 50 V typical output clamp voltage for inductive load flyback suppression. |+| 12 | OUT4 | output | Low-side driver output 4 with 0.5 A maximum capability and 50 V typical output clamp voltage for inductive load flyback suppression. |+| 13 | OUT3 | output | Low-side driver output 3 with 0.5 A maximum capability and 50 V typical output clamp voltage for inductive load flyback suppression. |+| 14 | OUT2 | output | Low-side driver output 2 with 0.5 A maximum capability and 50 V typical output clamp voltage for inductive load flyback suppression. |+| 15 | SFPD | input | Short Fault Protect Disable control input; VDD-tied enables current limiting mode on overcurrent; GND-tied enables immediate latch-off shutdown on overcurrent. |+| 16 | VDD | power_in | Single supply voltage input; 4.5 V to 5.5 V nominal operation with 2.5 V to 3.95 V undervoltage reset threshold. |+| 17 | GND | power_in | Analog ground connection point. |+| 18 | GND | power_in | Analog ground connection point. |+| 19 | GND | power_in | Analog ground connection point. |+| 20 | GND | power_in | Analog ground connection point. |+| 21 | N.C. | unconnected | No internal connection. |+| 22 | RESET | input | Active-low asynchronous reset input clearing SPI shift register and turning all outputs off; requires 160 ns minimum low pulse; includes internal pull-down. |+| 23 | OUT1 | output | Low-side driver output 1 with 0.5 A maximum capability and 50 V typical output clamp voltage for inductive load flyback suppression. |+| 24 | OUT0 | output | Low-side driver output 0 with 0.5 A maximum capability and 50 V typical output clamp voltage for inductive load flyback suppression. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | SO-24-300mil |+| Category | Power Supply Chip |+| Pins | 24 |++## CAD (KiCad official)++- Symbol: `E-L9823013TR`+- Footprint: `Package_SO:SO-24_5.3x15mm_P1.27mm`+- 3D model: SO-24-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.75 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `e-l9823013tr-etched.step` / `e-l9823013tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `e-l9823013tr.step` / `e-l9823013tr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884732355989504) (19 pp, sha256 `045398f1bc6a2a97`, retrieved 2026-10-01, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/e-l9823013tr-datasheet.pdf)
page.jsonadded+252@@ -0,0 +1,252 @@+{+ "slug": "e-l9823013tr",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics Power Distribution Switches, SO-24-300mil. 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160 ns minimum low time; shifts data on falling edge into shift register and changes SO on rising edge."+ },+ {+ "number": "4",+ "name": "SI",+ "type": "input",+ "description": "SPI serial data input; 8-bit instruction stream accepted on falling edge of SCLK with MSB first; logic level selects output on/off on CSB rising edge."+ },+ {+ "number": "5",+ "name": "GND",+ "type": "power_in",+ "description": "Analog ground connection point."+ },+ {+ "number": "6",+ "name": "GND",+ "type": "power_in",+ "description": "Analog ground connection point."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Analog ground connection point."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Analog ground connection point."+ },+ {+ "number": "9",+ "name": "SO",+ "type": "tri_state",+ "description": "Tri-state SPI serial output reporting drain status; remains high-impedance until CSB goes low; changes state on rising SCLK edge with 100 ns maximum propagation delay."+ },+ {+ "number": "10",+ "name": "CSB",+ "type": "input",+ "description": "Active-low chip select input enabling SPI communication; latches output control data on rising edge; must transition only when SCLK is low."+ },+ {+ "number": "11",+ "name": "OUT5",+ "type": "output",+ "description": "Low-side driver output 5 with 0.5 A maximum capability and 50 V typical output clamp voltage for inductive load flyback suppression."+ },+ {+ "number": "12",+ "name": "OUT4",+ "type": "output",+ "description": "Low-side driver output 4 with 0.5 A maximum capability and 50 V typical output clamp voltage for inductive load flyback suppression."+ },+ {+ "number": "13",+ "name": "OUT3",+ "type": "output",+ "description": "Low-side driver output 3 with 0.5 A maximum capability and 50 V typical output clamp voltage for inductive load flyback suppression."+ },+ {+ "number": "14",+ "name": "OUT2",+ "type": "output",+ "description": "Low-side driver output 2 with 0.5 A maximum capability and 50 V typical output clamp voltage for inductive load flyback suppression."+ },+ {+ "number": "15",+ "name": "SFPD",+ "type": "input",+ "description": "Short Fault Protect Disable control input; VDD-tied enables current limiting mode on overcurrent; GND-tied enables immediate latch-off shutdown on overcurrent."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Single supply voltage input; 4.5 V to 5.5 V nominal operation with 2.5 V to 3.95 V undervoltage reset threshold."+ },+ {+ "number": "17",+ "name": "GND",+ "type": "power_in",+ "description": "Analog ground connection point."+ },+ {+ "number": "18",+ "name": "GND",+ "type": "power_in",+ "description": "Analog ground connection point."+ },+ {+ "number": "19",+ "name": "GND",+ "type": "power_in",+ "description": "Analog ground connection point."+ },+ {+ "number": "20",+ "name": "GND",+ "type": "power_in",+ "description": "Analog ground connection point."+ },+ {+ "number": "21",+ "name": "N.C.",+ "type": "unconnected",+ "description": "No internal connection."+ },+ {+ "number": "22",+ "name": "RESET",+ "type": "input",+ "description": "Active-low asynchronous reset input clearing SPI shift register and turning all outputs off; requires 160 ns minimum low pulse; includes internal pull-down."+ },+ {+ "number": "23",+ "name": "OUT1",+ "type": "output",+ "description": "Low-side driver output 1 with 0.5 A maximum capability and 50 V typical output clamp voltage for inductive load flyback suppression."+ },+ {+ "number": "24",+ "name": "OUT0",+ "type": "output",+ "description": "Low-side driver output 0 with 0.5 A maximum capability and 50 V typical output clamp voltage for inductive load flyback suppression."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 19,+ "cost_usd": 0.1645,+ "at": "2026-10-01T18:05:11"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884732355989504",+ "pages": 19,+ "sha256": "045398f1bc6a2a97",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 24,+ "described": 24,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}