dsPIC33FJ64MC802-I/SO

@@ -8,33 +8,33 @@ dsPIC33FJ64MC802-I from Microchip Tech, in a SOIC-28-300mil. Pinout and pin desc  | Pin | Name | Type | Function | |---|---|---|---|-| 1 | MCLR | input | Master Clear active-low Reset input (Schmitt Trigger); also used for device programming and debugging. |-| 2 | AN0/VREF+/CN2/RA0 | bidirectional | PORTA I/O RA0 shared with analog input AN0, external ADC reference high VREF+ and change notification CN2. |-| 3 | AN1/VREF-/CN3/RA1 | bidirectional | PORTA I/O RA1 shared with analog input AN1, external ADC reference low VREF- and change notification CN3. |-| 4 | PGED1/AN2/C2IN-/RP0/CN4/RB0 | bidirectional | PORTB I/O RB0 with ICSP data PGED1, analog input AN2, comparator 2 negative input C2IN-, remappable pin RP0 and CN4. |-| 5 | PGEC1/AN3/C2IN+/RP1/CN5/RB1 | bidirectional | PORTB I/O RB1 with ICSP clock PGEC1, analog input AN3, comparator 2 positive input C2IN+, remappable pin RP1 and CN5. |-| 6 | AN4/C1IN-/RP2/CN6/RB2 | bidirectional | PORTB I/O RB2 with analog input AN4, comparator 1 negative input C1IN-, remappable pin RP2 and CN6. |-| 7 | AN5/C1IN+/RP3/CN7/RB3 | bidirectional | PORTB I/O RB3 with analog input AN5, comparator 1 positive input C1IN+, remappable pin RP3 and CN7. |-| 8 | VSS | power_in | Ground reference for logic and I/O pins. |-| 9 | OSC1/CLKI/CN30/RA2 | bidirectional | Oscillator crystal input or external clock input CLKI (ST buffer in RC mode, CMOS otherwise); also RA2 and CN30. |-| 10 | OSC2/CLKO/CN29/PMA0/RA3 | bidirectional | Oscillator crystal output, optionally CLKO in RC and EC modes; also RA3, CN29 and PMP address bit PMA0. |-| 11 | SOSCI/RP4/CN1/PMBE/RB4 | bidirectional | 32.768 kHz secondary oscillator crystal input; also RB4, remappable pin RP4, CN1 and PMP byte enable PMBE. |-| 12 | SOSCO/T1CK/CN0/PMA1/RA4 | bidirectional | 32.768 kHz secondary oscillator crystal output; also RA4, Timer1 external clock T1CK, CN0 and PMP address bit PMA1. |-| 13 | VDD | power_in | Positive supply for peripheral logic and I/O pins. |-| 14 | PGED3/ASDA1/RP5/CN27/PMD7/RB5 | bidirectional | PORTB I/O RB5 with ICSP data PGED3, alternate I2C1 data ASDA1, remappable pin RP5, CN27 and PMP data PMD7. |-| 15 | PGEC3/ASCL1/RP6/CN24/PMD6/RB6 | bidirectional | PORTB I/O RB6 with ICSP clock PGEC3, alternate I2C1 clock ASCL1, remappable pin RP6, CN24 and PMP data PMD6. |-| 16 | INT0/RP7/CN23/PMD5/RB7 | bidirectional | PORTB I/O RB7 with external interrupt 0 INT0, remappable pin RP7, CN23 and PMP data PMD5. |-| 17 | TCK/PWM2H1/SCL1/RP8/CN22/PMD4/RB8 | bidirectional | PORTB I/O RB8 with JTAG test clock TCK, PWM2 high output 1, I2C1 clock SCL1, remappable pin RP8, CN22 and PMD4. |-| 18 | TDO/PWM2L1/SDA1/RP9/CN21/PMD3/RB9 | bidirectional | PORTB I/O RB9 with JTAG test data output TDO, PWM2 low output 1, I2C1 data SDA1, remappable pin RP9, CN21 and PMD3. |-| 19 | VSS | power_in | Ground reference for logic and I/O pins. |-| 20 | VCAP | passive | CPU logic filter capacitor connection; needs a low-ESR (<5 ohm) 4.7 µF to 10 µF capacitor to ground and must not be connected to VDD. |-| 21 | PGED2/TDI/PWM1H3/RP10/CN16/PMD2/RB10 | bidirectional | PORTB I/O RB10 with ICSP data PGED2, JTAG test data input TDI, PWM1 high output 3, remappable pin RP10, CN16 and PMD2. |-| 22 | PGEC2/TMS/PWM1L3/RP11/CN15/PMD1/RB11 | bidirectional | PORTB I/O RB11 with ICSP clock PGEC2, JTAG test mode select TMS, PWM1 low output 3, remappable pin RP11, CN15 and PMD1. |-| 23 | PWM1H2/RP12/CN14/PMD0/RB12 | bidirectional | PORTB I/O RB12 with PWM1 high output 2, remappable pin RP12, CN14 and PMP data PMD0. |-| 24 | PWM1L2/RP13/CN13/PMRD/RB13 | bidirectional | PORTB I/O RB13 with PWM1 low output 2, remappable pin RP13, CN13 and PMP read strobe PMRD. |-| 25 | PWM1H1/RTCC/RP14/CN12/PMWR/RB14 | bidirectional | PORTB I/O RB14 with PWM1 high output 1, RTCC alarm output, remappable pin RP14, CN12 and PMP write strobe PMWR. |-| 26 | PWM1L1/RP15/CN11/PMCS1/RB15 | bidirectional | PORTB I/O RB15 with PWM1 low output 1, remappable pin RP15, CN11 and PMP chip select 1 PMCS1. |-| 27 | AVSS | power_in | Ground reference for analog modules. |+| 1 | MCLR | input | Master Clear input; active-low device Reset, also used for programming and debugging. |+| 2 | AN0/VREF+/CN2/RA0 | bidirectional | PORTA I/O RA0 with analog input AN0, external voltage reference (high) input VREF+ and change notification CN2. |+| 3 | AN1/VREF-/CN3/RA1 | bidirectional | PORTA I/O RA1 with analog input AN1, external voltage reference (low) input VREF- and change notification CN3. |+| 4 | PGED1/AN2/C2IN-/RP0/CN4/RB0 | bidirectional | PORTB I/O RB0 with ICSP data channel 1 (PGED1), AN2, comparator 2 negative input, remappable RP0 and CN4. |+| 5 | PGEC1/AN3/C2IN+/RP1/CN5/RB1 | bidirectional | PORTB I/O RB1 with ICSP clock channel 1 (PGEC1), AN3, comparator 2 positive input, remappable RP1 and CN5. |+| 6 | AN4/C1IN-/RP2/CN6/RB2 | bidirectional | PORTB I/O RB2 with AN4, comparator 1 negative input, remappable RP2 and CN6. |+| 7 | AN5/C1IN+/RP3/CN7/RB3 | bidirectional | PORTB I/O RB3 with AN5, comparator 1 positive input, remappable RP3 and CN7. |+| 8 | VSS | power_in | Ground reference for logic and I/O pins; must always be connected. |+| 9 | OSC1/CLKI/CN30/RA2 | bidirectional | Oscillator crystal input or external clock input CLKI, shared with PORTA RA2 and CN30. |+| 10 | OSC2/CLKO/CN29/PMA0/RA3 | bidirectional | Oscillator crystal output or CLKO, shared with PORTA RA3, CN29 and Parallel Master Port address bit PMA0. |+| 11 | SOSCI/RP4/CN1/PMBE/RB4 | bidirectional | 32.768 kHz secondary oscillator crystal input shared with PORTB RB4, remappable RP4, CN1 and PMP byte enable PMBE. |+| 12 | SOSCO/T1CK/CN0/PMA1/RA4 | bidirectional | 32.768 kHz secondary oscillator crystal output shared with PORTA RA4, Timer1 clock T1CK, CN0 and PMP address PMA1. |+| 13 | VDD | power_in | Positive supply for peripheral logic and I/O pins (3.0V to 3.6V operation); must always be connected. |+| 14 | PGED3/ASDA1/RP5/CN27/PMD7/RB5 | bidirectional | PORTB I/O RB5 with ICSP data channel 3 (PGED3), alternate I2C1 data ASDA1, remappable RP5, CN27 and PMP data PMD7. |+| 15 | PGEC3/ASCL1/RP6/CN24/PMD6/RB6 | bidirectional | PORTB I/O RB6 with ICSP clock channel 3 (PGEC3), alternate I2C1 clock ASCL1, remappable RP6, CN24 and PMP data PMD6. |+| 16 | INT0/RP7/CN23/PMD5/RB7 | bidirectional | PORTB I/O RB7 with external interrupt 0 (INT0), remappable RP7, CN23 and PMP data PMD5. |+| 17 | TCK/PWM2H1/SCL1/RP8/CN22/PMD4/RB8 | bidirectional | PORTB I/O RB8 with JTAG clock TCK, PWM2 high output 1, I2C1 clock SCL1, remappable RP8, CN22 and PMD4. |+| 18 | TDO/PWM2L1/SDA1/RP9/CN21/PMD3/RB9 | bidirectional | PORTB I/O RB9 with JTAG data out TDO, PWM2 low output 1, I2C1 data SDA1, remappable RP9, CN21 and PMD3. |+| 19 | VSS | power_in | Ground reference for logic and I/O pins; must always be connected. |+| 20 | VCAP | passive | CPU logic filter capacitor connection; needs a low-ESR (<5 ohm) 4.7 uF to 10 uF capacitor to ground and must not be connected to VDD. |+| 21 | PGED2/TDI/PWM1H3/RP10/CN16/PMD2/RB10 | bidirectional | PORTB I/O RB10 with ICSP data channel 2 (PGED2), JTAG TDI, PWM1 high output 3, remappable RP10, CN16 and PMD2. |+| 22 | PGEC2/TMS/PWM1L3/RP11/CN15/PMD1/RB11 | bidirectional | PORTB I/O RB11 with ICSP clock channel 2 (PGEC2), JTAG TMS, PWM1 low output 3, remappable RP11, CN15 and PMD1. |+| 23 | PWM1H2/RP12/CN14/PMD0/RB12 | bidirectional | PORTB I/O RB12 with PWM1 high output 2, remappable RP12, CN14 and PMP data PMD0. |+| 24 | PWM1L2/RP13/CN13/PMRD/RB13 | bidirectional | PORTB I/O RB13 with PWM1 low output 2, remappable RP13, CN13 and PMP read strobe PMRD. |+| 25 | PWM1H1/RTCC/RP14/CN12/PMWR/RB14 | bidirectional | PORTB I/O RB14 with PWM1 high output 1, RTCC alarm output, remappable RP14, CN12 and PMP write strobe PMWR. |+| 26 | PWM1L1/RP15/CN11/PMCS1/RB15 | bidirectional | PORTB I/O RB15 with PWM1 low output 1, remappable RP15, CN11 and PMP chip select PMCS1. |+| 27 | AVSS | power_in | Ground reference for analog modules; must be connected regardless of ADC use. | | 28 | AVDD | power_in | Positive supply for analog modules; must be connected at all times. |  ## Key specifications@@ -54,8 +54,8 @@ Limits as printed in the datasheet (page.json `metadata.characteristics` carries |---|---|---|---|---|---|---|---| | Supply Voltage | VDD | 3 |  | 3.6 | V | Industrial and Extended | 359 | | RAM Data Retention Voltage | VDR | 1.8 |  |  | V |  | 359 |-| VDD Rise Rate to ensure internal Power-on Reset signal | SVDD | 0.03 |  |  | V/ms | 0-3.0V in 0.1s | 359 |-| Operating temperature | TA | -40 |  | 85 | °C | Industrial | 359 |+| Operating temperature (Industrial) | TA | -40 |  | 85 | °C | Industrial | 359 |+| VDD Rise Rate (POR) | SVDD | 0.03 |  |  | V/ms | 0-3.0V in 0.1s | 359 |  ## CAD (KiCad official) @@ -68,7 +68,7 @@ Limits as printed in the datasheet (page.json `metadata.characteristics` carries  Data extracted from the manufacturer datasheet, not a distributor listing: -- **Datasheet:** [Microchip Tech datasheet](docs/dspic33fj64mc802-i-so-datasheet.pdf) (460 pp, sha256 `28337a1943388de8`, retrieved 2026-11-12, tier: manufacturer)+- **Datasheet:** [Microchip Tech datasheet](https://ww1.microchip.com/downloads/en/DeviceDoc/70291G.pdf) (460 pp, sha256 `28337a1943388de8`, retrieved 2026-11-13, tier: manufacturer) - **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - **CAD:** KiCad official libraries (CC-BY-SA 4.0). 

@@ -1,6 +1,6 @@ {   "slug": "dspic33fj64mc802-i-so",-  "version": "0.1.0",+  "version": "0.1.1",   "type": "component",   "description": "Microchip Tech Digital Signal Processors / Controllers (DSPs/DSCs), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",   "tags": [@@ -28,8 +28,7 @@     "viewers/symbol.html",     "viewers/footprint.html",     "dspic33fj64mc802-i-so-hero.glb",-    "dspic33fj64mc802-i-so-hero.overlay.json",-    "dspic33fj64mc802-i-so-etched.glb"+    "dspic33fj64mc802-i-so-hero.overlay.json"   ],   "component": {     "mpn": "dsPIC33FJ64MC802-I/SO",@@ -38,12 +37,12 @@     "pin_count": 28,     "category": "Single Chip Microcomputer/Microcontroller",     "subcategory": "Digital Signal Processors / Controllers (DSPs/DSCs)",-    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/46faec341b5eb29c974d9c1240267c41.pdf",+    "datasheet": "https://ww1.microchip.com/downloads/en/DeviceDoc/70291G.pdf",     "parts": {       "symbol": "dspic33fj64mc802-i-so.kicad_sym",       "footprint": "dspic33fj64mc802-i-so.kicad_mod",       "model_3d": "dspic33fj64mc802-i-so-hero.glb",-      "model_3d_plain": "dspic33fj64mc802-i-so-etched.glb",+      "model_3d_plain": "dspic33fj64mc802-i-so.glb",       "model_3d_step": "dspic33fj64mc802-i-so-etched.step",       "model_3d_step_plain": "dspic33fj64mc802-i-so.step",       "lbr": "dspic33fj64mc802-i-so.lbr"@@ -54,12 +53,11 @@       "mouser": "579-DSPIC364MC802ISO"     },     "distributor_check": {-      "checked_at": "2026-11-12T17:57:47Z",+      "checked_at": "2026-11-13T00:53:06Z",       "source": "Component Ocean /api/assign-pns",       "digikey": {         "pn": "DSPIC33FJ64MC802-I/SO-ND",-        "status": "found",-        "lifecycle": "Active"+        "status": "found"       },       "mouser": {         "pn": "579-DSPIC364MC802ISO",@@ -72,163 +70,163 @@         "number": "1",         "name": "MCLR",         "type": "input",-        "description": "Master Clear active-low Reset input (Schmitt Trigger); also used for device programming and debugging."+        "description": "Master Clear input; active-low device Reset, also used for programming and debugging."       },       {         "number": "2",         "name": "AN0/VREF+/CN2/RA0",         "type": "bidirectional",-        "description": "PORTA I/O RA0 shared with analog input AN0, external ADC reference high VREF+ and change notification CN2."+        "description": "PORTA I/O RA0 with analog input AN0, external voltage reference (high) input VREF+ and change notification CN2."       },       {         "number": "3",         "name": "AN1/VREF-/CN3/RA1",         "type": "bidirectional",-        "description": "PORTA I/O RA1 shared with analog input AN1, external ADC reference low VREF- and change notification CN3."+        "description": "PORTA I/O RA1 with analog input AN1, external voltage reference (low) input VREF- and change notification CN3."       },       {         "number": "4",         "name": "PGED1/AN2/C2IN-/RP0/CN4/RB0",         "type": "bidirectional",-        "description": "PORTB I/O RB0 with ICSP data PGED1, analog input AN2, comparator 2 negative input C2IN-, remappable pin RP0 and CN4."+        "description": "PORTB I/O RB0 with ICSP data channel 1 (PGED1), AN2, comparator 2 negative input, remappable RP0 and CN4."       },       {         "number": "5",         "name": "PGEC1/AN3/C2IN+/RP1/CN5/RB1",         "type": "bidirectional",-        "description": "PORTB I/O RB1 with ICSP clock PGEC1, analog input AN3, comparator 2 positive input C2IN+, remappable pin RP1 and CN5."+        "description": "PORTB I/O RB1 with ICSP clock channel 1 (PGEC1), AN3, comparator 2 positive input, remappable RP1 and CN5."       },       {         "number": "6",         "name": "AN4/C1IN-/RP2/CN6/RB2",         "type": "bidirectional",-        "description": "PORTB I/O RB2 with analog input AN4, comparator 1 negative input C1IN-, remappable pin RP2 and CN6."+        "description": "PORTB I/O RB2 with AN4, comparator 1 negative input, remappable RP2 and CN6."       },       {         "number": "7",         "name": "AN5/C1IN+/RP3/CN7/RB3",         "type": "bidirectional",-        "description": "PORTB I/O RB3 with analog input AN5, comparator 1 positive input C1IN+, remappable pin RP3 and CN7."+        "description": "PORTB I/O RB3 with AN5, comparator 1 positive input, remappable RP3 and CN7."       },       {         "number": "8",         "name": "VSS",         "type": "power_in",-        "description": "Ground reference for logic and I/O pins."+        "description": "Ground reference for logic and I/O pins; must always be connected."       },       {         "number": "9",         "name": "OSC1/CLKI/CN30/RA2",         "type": "bidirectional",-        "description": "Oscillator crystal input or external clock input CLKI (ST buffer in RC mode, CMOS otherwise); also RA2 and CN30."+        "description": "Oscillator crystal input or external clock input CLKI, shared with PORTA RA2 and CN30."       },       {         "number": "10",         "name": "OSC2/CLKO/CN29/PMA0/RA3",         "type": "bidirectional",-        "description": "Oscillator crystal output, optionally CLKO in RC and EC modes; also RA3, CN29 and PMP address bit PMA0."+        "description": "Oscillator crystal output or CLKO, shared with PORTA RA3, CN29 and Parallel Master Port address bit PMA0."       },       {         "number": "11",         "name": "SOSCI/RP4/CN1/PMBE/RB4",         "type": "bidirectional",-        "description": "32.768 kHz secondary oscillator crystal input; also RB4, remappable pin RP4, CN1 and PMP byte enable PMBE."+        "description": "32.768 kHz secondary oscillator crystal input shared with PORTB RB4, remappable RP4, CN1 and PMP byte enable PMBE."       },       {         "number": "12",         "name": "SOSCO/T1CK/CN0/PMA1/RA4",         "type": "bidirectional",-        "description": "32.768 kHz secondary oscillator crystal output; also RA4, Timer1 external clock T1CK, CN0 and PMP address bit PMA1."+        "description": "32.768 kHz secondary oscillator crystal output shared with PORTA RA4, Timer1 clock T1CK, CN0 and PMP address PMA1."       },       {         "number": "13",         "name": "VDD",         "type": "power_in",-        "description": "Positive supply for peripheral logic and I/O pins."+        "description": "Positive supply for peripheral logic and I/O pins (3.0V to 3.6V operation); must always be connected."       },       {         "number": "14",         "name": "PGED3/ASDA1/RP5/CN27/PMD7/RB5",         "type": "bidirectional",-        "description": "PORTB I/O RB5 with ICSP data PGED3, alternate I2C1 data ASDA1, remappable pin RP5, CN27 and PMP data PMD7."+        "description": "PORTB I/O RB5 with ICSP data channel 3 (PGED3), alternate I2C1 data ASDA1, remappable RP5, CN27 and PMP data PMD7."       },       {         "number": "15",         "name": "PGEC3/ASCL1/RP6/CN24/PMD6/RB6",         "type": "bidirectional",-        "description": "PORTB I/O RB6 with ICSP clock PGEC3, alternate I2C1 clock ASCL1, remappable pin RP6, CN24 and PMP data PMD6."+        "description": "PORTB I/O RB6 with ICSP clock channel 3 (PGEC3), alternate I2C1 clock ASCL1, remappable RP6, CN24 and PMP data PMD6."       },       {         "number": "16",         "name": "INT0/RP7/CN23/PMD5/RB7",         "type": "bidirectional",-        "description": "PORTB I/O RB7 with external interrupt 0 INT0, remappable pin RP7, CN23 and PMP data PMD5."+        "description": "PORTB I/O RB7 with external interrupt 0 (INT0), remappable RP7, CN23 and PMP data PMD5."       },       {         "number": "17",         "name": "TCK/PWM2H1/SCL1/RP8/CN22/PMD4/RB8",         "type": "bidirectional",-        "description": "PORTB I/O RB8 with JTAG test clock TCK, PWM2 high output 1, I2C1 clock SCL1, remappable pin RP8, CN22 and PMD4."+        "description": "PORTB I/O RB8 with JTAG clock TCK, PWM2 high output 1, I2C1 clock SCL1, remappable RP8, CN22 and PMD4."       },       {         "number": "18",         "name": "TDO/PWM2L1/SDA1/RP9/CN21/PMD3/RB9",         "type": "bidirectional",-        "description": "PORTB I/O RB9 with JTAG test data output TDO, PWM2 low output 1, I2C1 data SDA1, remappable pin RP9, CN21 and PMD3."+        "description": "PORTB I/O RB9 with JTAG data out TDO, PWM2 low output 1, I2C1 data SDA1, remappable RP9, CN21 and PMD3."       },       {         "number": "19",         "name": "VSS",         "type": "power_in",-        "description": "Ground reference for logic and I/O pins."+        "description": "Ground reference for logic and I/O pins; must always be connected."       },       {         "number": "20",         "name": "VCAP",         "type": "passive",-        "description": "CPU logic filter capacitor connection; needs a low-ESR (<5 ohm) 4.7 µF to 10 µF capacitor to ground and must not be connected to VDD."+        "description": "CPU logic filter capacitor connection; needs a low-ESR (<5 ohm) 4.7 uF to 10 uF capacitor to ground and must not be connected to VDD."       },       {         "number": "21",         "name": "PGED2/TDI/PWM1H3/RP10/CN16/PMD2/RB10",         "type": "bidirectional",-        "description": "PORTB I/O RB10 with ICSP data PGED2, JTAG test data input TDI, PWM1 high output 3, remappable pin RP10, CN16 and PMD2."+        "description": "PORTB I/O RB10 with ICSP data channel 2 (PGED2), JTAG TDI, PWM1 high output 3, remappable RP10, CN16 and PMD2."       },       {         "number": "22",         "name": "PGEC2/TMS/PWM1L3/RP11/CN15/PMD1/RB11",         "type": "bidirectional",-        "description": "PORTB I/O RB11 with ICSP clock PGEC2, JTAG test mode select TMS, PWM1 low output 3, remappable pin RP11, CN15 and PMD1."+        "description": "PORTB I/O RB11 with ICSP clock channel 2 (PGEC2), JTAG TMS, PWM1 low output 3, remappable RP11, CN15 and PMD1."       },       {         "number": "23",         "name": "PWM1H2/RP12/CN14/PMD0/RB12",         "type": "bidirectional",-        "description": "PORTB I/O RB12 with PWM1 high output 2, remappable pin RP12, CN14 and PMP data PMD0."+        "description": "PORTB I/O RB12 with PWM1 high output 2, remappable RP12, CN14 and PMP data PMD0."       },       {         "number": "24",         "name": "PWM1L2/RP13/CN13/PMRD/RB13",         "type": "bidirectional",-        "description": "PORTB I/O RB13 with PWM1 low output 2, remappable pin RP13, CN13 and PMP read strobe PMRD."+        "description": "PORTB I/O RB13 with PWM1 low output 2, remappable RP13, CN13 and PMP read strobe PMRD."       },       {         "number": "25",         "name": "PWM1H1/RTCC/RP14/CN12/PMWR/RB14",         "type": "bidirectional",-        "description": "PORTB I/O RB14 with PWM1 high output 1, RTCC alarm output, remappable pin RP14, CN12 and PMP write strobe PMWR."+        "description": "PORTB I/O RB14 with PWM1 high output 1, RTCC alarm output, remappable RP14, CN12 and PMP write strobe PMWR."       },       {         "number": "26",         "name": "PWM1L1/RP15/CN11/PMCS1/RB15",         "type": "bidirectional",-        "description": "PORTB I/O RB15 with PWM1 low output 1, remappable pin RP15, CN11 and PMP chip select 1 PMCS1."+        "description": "PORTB I/O RB15 with PWM1 low output 1, remappable RP15, CN11 and PMP chip select PMCS1."       },       {         "number": "27",         "name": "AVSS",         "type": "power_in",-        "description": "Ground reference for analog modules."+        "description": "Ground reference for analog modules; must be connected regardless of ADC use."       },       {         "number": "28",@@ -248,14 +246,14 @@         "consensus": "agreed",         "guards": "pin_guards 0.1: passed",         "guard_notes": [-          "extractor flagged: The 28-pin SPDIP/SOIC pin diagram on page 3 is captioned under dsPIC33FJ32MC302. The dsPIC33FJ64MC80; Pin numbers were reconstructed from the text order of the page 3 diagram, because the extracted text; Pin types are inferred for KiCad ERC. Multiplexed pins are typed bidirectional because they include "+          "extractor flagged: The 28-pin SPDIP/SOIC pin diagram on page 3 is captioned with dsPIC33FJ32MC302 and the extracted tex; The datasheet's 28-pin SPDIP/SOIC diagram is shared across the family. dsPIC33FJ64MC802 is listed in; Pin descriptions are condensed from Table 1-1 (pages 13-15) and the page 3 diagram rather than quote"         ],         "pages_sent": 70,-        "cost_usd": 0.3707,-        "at": "2026-11-12T17:57:29"+        "cost_usd": 0.3722,+        "at": "2026-11-13T00:52:43"       },       "datasheet": {-        "url": "https://datasheet.lcsc.com/datasheet/pdf/46faec341b5eb29c974d9c1240267c41.pdf",+        "url": "https://ww1.microchip.com/downloads/en/DeviceDoc/70291G.pdf",         "pages": 460,         "sha256": "28337a1943388de8",         "source_tier": "mfr"@@ -289,7 +287,7 @@         "centre_offset_mm": 0.0,         "footprint_binding": "identity",         "sha256": "b889a13dbe9ec59e79fa9f1b5118b00bfa54f9582392335ff3365b64afc264b1",-        "checked": "2026-11-12",+        "checked": "2026-11-13",         "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       },       {@@ -307,13 +305,13 @@         "zmin_mm": -0.0,         "centre_offset_mm": 0.0,         "footprint_binding": "identity",-        "sha256": "fa4235031c69dc3abaa5baf7273c00a8c2233ad42900d35144baebfc7ddee0f7",-        "checked": "2026-11-12",+        "sha256": "23384278d25fb8a9257f1df5828575bdace20854da86badb1aa94fc8f3a947fa",+        "checked": "2026-11-13",         "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       }     ],     "package_dims": {-      "package_code": "SO",+      "package_code": "SO (28-Lead SOIC, 7.50 mm body, Microchip drawing C04-052B)",       "source_page": 431,       "D": {         "nom_mm": 17.9,

@@ -4,7 +4,7 @@   "slug": "dspic33fj64mc802-i-so",   "title": "dsPIC33FJ64MC802-I/SO",   "brief": "Microchip Tech Digital Signal Processors / Controllers (DSPs/DSCs), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",-  "version": "0.1.0",+  "version": "0.1.1",   "license": "CC-BY-SA-4.0",   "tags": [     "component",@@ -20,12 +20,12 @@     "pin_count": 28,     "category": "Single Chip Microcomputer/Microcontroller",     "subcategory": "Digital Signal Processors / Controllers (DSPs/DSCs)",-    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/46faec341b5eb29c974d9c1240267c41.pdf",+    "datasheet": "https://ww1.microchip.com/downloads/en/DeviceDoc/70291G.pdf",     "parts": {       "symbol": "dspic33fj64mc802-i-so.kicad_sym",       "footprint": "dspic33fj64mc802-i-so.kicad_mod",       "model_3d": "dspic33fj64mc802-i-so-hero.glb",-      "model_3d_plain": "dspic33fj64mc802-i-so-etched.glb",+      "model_3d_plain": "dspic33fj64mc802-i-so.glb",       "model_3d_step": "dspic33fj64mc802-i-so-etched.step",       "model_3d_step_plain": "dspic33fj64mc802-i-so.step",       "lbr": "dspic33fj64mc802-i-so.lbr"@@ -36,12 +36,11 @@       "mouser": "579-DSPIC364MC802ISO"     },     "distributor_check": {-      "checked_at": "2026-11-12T17:57:47Z",+      "checked_at": "2026-11-13T00:53:06Z",       "source": "Component Ocean /api/assign-pns",       "digikey": {         "pn": "DSPIC33FJ64MC802-I/SO-ND",-        "status": "found",-        "lifecycle": "Active"+        "status": "found"       },       "mouser": {         "pn": "579-DSPIC364MC802ISO",@@ -54,163 +53,163 @@         "number": "1",         "name": "MCLR",         "type": "input",-        "description": "Master Clear active-low Reset input (Schmitt Trigger); also used for device programming and debugging."+        "description": "Master Clear input; active-low device Reset, also used for programming and debugging."       },       {         "number": "2",         "name": "AN0/VREF+/CN2/RA0",         "type": "bidirectional",-        "description": "PORTA I/O RA0 shared with analog input AN0, external ADC reference high VREF+ and change notification CN2."+        "description": "PORTA I/O RA0 with analog input AN0, external voltage reference (high) input VREF+ and change notification CN2."       },       {         "number": "3",         "name": "AN1/VREF-/CN3/RA1",         "type": "bidirectional",-        "description": "PORTA I/O RA1 shared with analog input AN1, external ADC reference low VREF- and change notification CN3."+        "description": "PORTA I/O RA1 with analog input AN1, external voltage reference (low) input VREF- and change notification CN3."       },       {         "number": "4",         "name": "PGED1/AN2/C2IN-/RP0/CN4/RB0",         "type": "bidirectional",-        "description": "PORTB I/O RB0 with ICSP data PGED1, analog input AN2, comparator 2 negative input C2IN-, remappable pin RP0 and CN4."+        "description": "PORTB I/O RB0 with ICSP data channel 1 (PGED1), AN2, comparator 2 negative input, remappable RP0 and CN4."       },       {         "number": "5",         "name": "PGEC1/AN3/C2IN+/RP1/CN5/RB1",         "type": "bidirectional",-        "description": "PORTB I/O RB1 with ICSP clock PGEC1, analog input AN3, comparator 2 positive input C2IN+, remappable pin RP1 and CN5."+        "description": "PORTB I/O RB1 with ICSP clock channel 1 (PGEC1), AN3, comparator 2 positive input, remappable RP1 and CN5."       },       {         "number": "6",         "name": "AN4/C1IN-/RP2/CN6/RB2",         "type": "bidirectional",-        "description": "PORTB I/O RB2 with analog input AN4, comparator 1 negative input C1IN-, remappable pin RP2 and CN6."+        "description": "PORTB I/O RB2 with AN4, comparator 1 negative input, remappable RP2 and CN6."       },       {         "number": "7",         "name": "AN5/C1IN+/RP3/CN7/RB3",         "type": "bidirectional",-        "description": "PORTB I/O RB3 with analog input AN5, comparator 1 positive input C1IN+, remappable pin RP3 and CN7."+        "description": "PORTB I/O RB3 with AN5, comparator 1 positive input, remappable RP3 and CN7."       },       {         "number": "8",         "name": "VSS",         "type": "power_in",-        "description": "Ground reference for logic and I/O pins."+        "description": "Ground reference for logic and I/O pins; must always be connected."       },       {         "number": "9",         "name": "OSC1/CLKI/CN30/RA2",         "type": "bidirectional",-        "description": "Oscillator crystal input or external clock input CLKI (ST buffer in RC mode, CMOS otherwise); also RA2 and CN30."+        "description": "Oscillator crystal input or external clock input CLKI, shared with PORTA RA2 and CN30."       },       {         "number": "10",         "name": "OSC2/CLKO/CN29/PMA0/RA3",         "type": "bidirectional",-        "description": "Oscillator crystal output, optionally CLKO in RC and EC modes; also RA3, CN29 and PMP address bit PMA0."+        "description": "Oscillator crystal output or CLKO, shared with PORTA RA3, CN29 and Parallel Master Port address bit PMA0."       },       {         "number": "11",         "name": "SOSCI/RP4/CN1/PMBE/RB4",         "type": "bidirectional",-        "description": "32.768 kHz secondary oscillator crystal input; also RB4, remappable pin RP4, CN1 and PMP byte enable PMBE."+        "description": "32.768 kHz secondary oscillator crystal input shared with PORTB RB4, remappable RP4, CN1 and PMP byte enable PMBE."       },       {         "number": "12",         "name": "SOSCO/T1CK/CN0/PMA1/RA4",         "type": "bidirectional",-        "description": "32.768 kHz secondary oscillator crystal output; also RA4, Timer1 external clock T1CK, CN0 and PMP address bit PMA1."+        "description": "32.768 kHz secondary oscillator crystal output shared with PORTA RA4, Timer1 clock T1CK, CN0 and PMP address PMA1."       },       {         "number": "13",         "name": "VDD",         "type": "power_in",-        "description": "Positive supply for peripheral logic and I/O pins."+        "description": "Positive supply for peripheral logic and I/O pins (3.0V to 3.6V operation); must always be connected."       },       {         "number": "14",         "name": "PGED3/ASDA1/RP5/CN27/PMD7/RB5",         "type": "bidirectional",-        "description": "PORTB I/O RB5 with ICSP data PGED3, alternate I2C1 data ASDA1, remappable pin RP5, CN27 and PMP data PMD7."+        "description": "PORTB I/O RB5 with ICSP data channel 3 (PGED3), alternate I2C1 data ASDA1, remappable RP5, CN27 and PMP data PMD7."       },       {         "number": "15",         "name": "PGEC3/ASCL1/RP6/CN24/PMD6/RB6",         "type": "bidirectional",-        "description": "PORTB I/O RB6 with ICSP clock PGEC3, alternate I2C1 clock ASCL1, remappable pin RP6, CN24 and PMP data PMD6."+        "description": "PORTB I/O RB6 with ICSP clock channel 3 (PGEC3), alternate I2C1 clock ASCL1, remappable RP6, CN24 and PMP data PMD6."       },       {         "number": "16",         "name": "INT0/RP7/CN23/PMD5/RB7",         "type": "bidirectional",-        "description": "PORTB I/O RB7 with external interrupt 0 INT0, remappable pin RP7, CN23 and PMP data PMD5."+        "description": "PORTB I/O RB7 with external interrupt 0 (INT0), remappable RP7, CN23 and PMP data PMD5."       },       {         "number": "17",         "name": "TCK/PWM2H1/SCL1/RP8/CN22/PMD4/RB8",         "type": "bidirectional",-        "description": "PORTB I/O RB8 with JTAG test clock TCK, PWM2 high output 1, I2C1 clock SCL1, remappable pin RP8, CN22 and PMD4."+        "description": "PORTB I/O RB8 with JTAG clock TCK, PWM2 high output 1, I2C1 clock SCL1, remappable RP8, CN22 and PMD4."       },       {         "number": "18",         "name": "TDO/PWM2L1/SDA1/RP9/CN21/PMD3/RB9",         "type": "bidirectional",-        "description": "PORTB I/O RB9 with JTAG test data output TDO, PWM2 low output 1, I2C1 data SDA1, remappable pin RP9, CN21 and PMD3."+        "description": "PORTB I/O RB9 with JTAG data out TDO, PWM2 low output 1, I2C1 data SDA1, remappable RP9, CN21 and PMD3."       },       {         "number": "19",         "name": "VSS",         "type": "power_in",-        "description": "Ground reference for logic and I/O pins."+        "description": "Ground reference for logic and I/O pins; must always be connected."       },       {         "number": "20",         "name": "VCAP",         "type": "passive",-        "description": "CPU logic filter capacitor connection; needs a low-ESR (<5 ohm) 4.7 µF to 10 µF capacitor to ground and must not be connected to VDD."+        "description": "CPU logic filter capacitor connection; needs a low-ESR (<5 ohm) 4.7 uF to 10 uF capacitor to ground and must not be connected to VDD."       },       {         "number": "21",         "name": "PGED2/TDI/PWM1H3/RP10/CN16/PMD2/RB10",         "type": "bidirectional",-        "description": "PORTB I/O RB10 with ICSP data PGED2, JTAG test data input TDI, PWM1 high output 3, remappable pin RP10, CN16 and PMD2."+        "description": "PORTB I/O RB10 with ICSP data channel 2 (PGED2), JTAG TDI, PWM1 high output 3, remappable RP10, CN16 and PMD2."       },       {         "number": "22",         "name": "PGEC2/TMS/PWM1L3/RP11/CN15/PMD1/RB11",         "type": "bidirectional",-        "description": "PORTB I/O RB11 with ICSP clock PGEC2, JTAG test mode select TMS, PWM1 low output 3, remappable pin RP11, CN15 and PMD1."+        "description": "PORTB I/O RB11 with ICSP clock channel 2 (PGEC2), JTAG TMS, PWM1 low output 3, remappable RP11, CN15 and PMD1."       },       {         "number": "23",         "name": "PWM1H2/RP12/CN14/PMD0/RB12",         "type": "bidirectional",-        "description": "PORTB I/O RB12 with PWM1 high output 2, remappable pin RP12, CN14 and PMP data PMD0."+        "description": "PORTB I/O RB12 with PWM1 high output 2, remappable RP12, CN14 and PMP data PMD0."       },       {         "number": "24",         "name": "PWM1L2/RP13/CN13/PMRD/RB13",         "type": "bidirectional",-        "description": "PORTB I/O RB13 with PWM1 low output 2, remappable pin RP13, CN13 and PMP read strobe PMRD."+        "description": "PORTB I/O RB13 with PWM1 low output 2, remappable RP13, CN13 and PMP read strobe PMRD."       },       {         "number": "25",         "name": "PWM1H1/RTCC/RP14/CN12/PMWR/RB14",         "type": "bidirectional",-        "description": "PORTB I/O RB14 with PWM1 high output 1, RTCC alarm output, remappable pin RP14, CN12 and PMP write strobe PMWR."+        "description": "PORTB I/O RB14 with PWM1 high output 1, RTCC alarm output, remappable RP14, CN12 and PMP write strobe PMWR."       },       {         "number": "26",         "name": "PWM1L1/RP15/CN11/PMCS1/RB15",         "type": "bidirectional",-        "description": "PORTB I/O RB15 with PWM1 low output 1, remappable pin RP15, CN11 and PMP chip select 1 PMCS1."+        "description": "PORTB I/O RB15 with PWM1 low output 1, remappable RP15, CN11 and PMP chip select PMCS1."       },       {         "number": "27",         "name": "AVSS",         "type": "power_in",-        "description": "Ground reference for analog modules."+        "description": "Ground reference for analog modules; must be connected regardless of ADC use."       },       {         "number": "28",@@ -230,14 +229,14 @@         "consensus": "agreed",         "guards": "pin_guards 0.1: passed",         "guard_notes": [-          "extractor flagged: The 28-pin SPDIP/SOIC pin diagram on page 3 is captioned under dsPIC33FJ32MC302. The dsPIC33FJ64MC80; Pin numbers were reconstructed from the text order of the page 3 diagram, because the extracted text; Pin types are inferred for KiCad ERC. Multiplexed pins are typed bidirectional because they include "+          "extractor flagged: The 28-pin SPDIP/SOIC pin diagram on page 3 is captioned with dsPIC33FJ32MC302 and the extracted tex; The datasheet's 28-pin SPDIP/SOIC diagram is shared across the family. dsPIC33FJ64MC802 is listed in; Pin descriptions are condensed from Table 1-1 (pages 13-15) and the page 3 diagram rather than quote"         ],         "pages_sent": 70,-        "cost_usd": 0.3707,-        "at": "2026-11-12T17:57:29"+        "cost_usd": 0.3722,+        "at": "2026-11-13T00:52:43"       },       "datasheet": {-        "url": "https://datasheet.lcsc.com/datasheet/pdf/46faec341b5eb29c974d9c1240267c41.pdf",+        "url": "https://ww1.microchip.com/downloads/en/DeviceDoc/70291G.pdf",         "pages": 460,         "sha256": "28337a1943388de8",         "source_tier": "mfr"@@ -271,7 +270,7 @@         "centre_offset_mm": 0,         "footprint_binding": "identity",         "sha256": "b889a13dbe9ec59e79fa9f1b5118b00bfa54f9582392335ff3365b64afc264b1",-        "checked": "2026-11-12",+        "checked": "2026-11-13",         "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       },       {@@ -289,13 +288,13 @@         "zmin_mm": 0,         "centre_offset_mm": 0,         "footprint_binding": "identity",-        "sha256": "fa4235031c69dc3abaa5baf7273c00a8c2233ad42900d35144baebfc7ddee0f7",-        "checked": "2026-11-12",+        "sha256": "23384278d25fb8a9257f1df5828575bdace20854da86badb1aa94fc8f3a947fa",+        "checked": "2026-11-13",         "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       }     ],     "package_dims": {-      "package_code": "SO",+      "package_code": "SO (28-Lead SOIC, 7.50 mm body, Microchip drawing C04-052B)",       "source_page": 431,       "D": {         "nom_mm": 17.9,@@ -440,10 +439,11 @@     "viewers/symbol.html",     "viewers/footprint.html",     "dspic33fj64mc802-i-so-hero.glb",-    "dspic33fj64mc802-i-so-hero.overlay.json",-    "dspic33fj64mc802-i-so-etched.glb"+    "dspic33fj64mc802-i-so-hero.overlay.json"   ],   "visibility": {     "public": true-  }+  },+  "description": "Microchip Tech Digital Signal Processors / Controllers (DSPs/DSCs), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "org": "adom" }\ No newline at end of file