component
dsPIC33EP16GS502-I/MM
Public Made by Adomby adom
Microchip Tech MICROCHIP, QFN-28-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.md+90docs/dspic33ep16gs502-i-mm-datasheet.pdfdocs/hero.pngdspic33ep16gs502-i-mm-hero.glbdspic33ep16gs502-i-mm-hero.overlay.json+713dspic33ep16gs502-i-mm.glbdspic33ep16gs502-i-mm.kicad_mod+397dspic33ep16gs502-i-mm.kicad_sym+129dspic33ep16gs502-i-mm.lbr+206dspic33ep16gs502-i-mm.step+13200package.json+368page.json+373viewers/footprint.html+1viewers/symbol.html+1README.mdadded+90@@ -0,0 +1,90 @@+# dsPIC33EP16GS502-I++**Microchip Tech** · MICROCHIP · QFN-28-EP(6x6)++dsPIC33EP16GS502-I from Microchip Tech, in a QFN-28-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2 | input | Analog input AN2 (also PGA1P3, PGA2P2, CMP1C, CMP2A, PORTA RA2); analog functions are enabled by default after Reset and disable the digital input buffer until ANSELx is cleared. |+| 2 | AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0 | input | Analog input AN3 (also PGA2P3, CMP1D, CMP2B) shared with remappable RP32 and PORTB RB0; ANSELx must be cleared before the digital function can be used. |+| 3 | AN4/CMP2C/CMP3A/ISRC4/RP41/RB9 | input | Analog input AN4 (also CMP2C, CMP3A, constant-current output ISRC4) shared with remappable RP41 and PORTB RB9. |+| 4 | AN5/CMP2D/CMP3B/ISRC3/RP42/RB10 | input | Analog input AN5 (also CMP2D, CMP3B, constant-current output ISRC3) shared with remappable RP42 and PORTB RB10. |+| 5 | VSS | power_in | Ground reference for logic and I/O pins. |+| 6 | OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1 | input | Oscillator crystal input (ST buffer in RC mode, CMOS otherwise) or external clock source input CLKI, also shared with AN6 and PORTB RB1. |+| 7 | OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2 | bidirectional | Oscillator crystal output connecting to a crystal in XT/HS mode, optionally CLKO in RC/EC modes (function selected by OSCIOFNC); also shared with AN7, PGA1N2 and PORTB RB2. |+| 8 | PGED2/AN18/DACOUT1/INT0/RP35/RB3 | bidirectional | Data I/O pin for programming/debugging communication channel 2; also shared with AN18, DACOUT1, external interrupt INT0 (not remappable) and RB3. |+| 9 | PGEC2/ADTRG31/EXTREF1/RP36/RB4 | input | Clock input pin for programming/debugging communication channel 2; also shared with external ADC trigger ADTRG31 and external reference input EXTREF1. |+| 10 | VDD | power_in | Positive supply for peripheral logic and I/O pins, specified for 3.0 V to 3.6 V operation. |+| 11 | PGED3/SDA2/FLT31/RP40/RB8 | bidirectional | Data I/O pin for programming/debugging communication channel 3; also shared with I2C2 data SDA2, Class B PWM Fault input FLT31 (not remappable) and RB8. |+| 12 | PGEC3/SCL2/RP47/RB15 | input | Clock input pin for programming/debugging communication channel 3; also shared with I2C2 clock SCL2 and PORTB RB15. |+| 13 | TDO/AN19/PGA2N2/RP37/RB5 | output | JTAG test data output pin; also shared with AN19, PGA2N2 negative input and PORTB RB5. |+| 14 | PGED1/TDI/AN20/SCL1/RP38/RB6 | bidirectional | Data I/O pin for programming/debugging communication channel 1; also shared with JTAG test data input TDI, AN20, I2C1 clock SCL1 and PORTB RB6. |+| 15 | PGEC1/AN21/SDA1/RP39/RB7 | input | Clock input pin for programming/debugging communication channel 1; also shared with AN21, I2C1 data SDA1 and PORTB RB7. |+| 16 | VSS | power_in | Ground reference for logic and I/O pins. |+| 17 | VCAP | power_out | CPU logic filter capacitor connection; requires a low-ESR (<0.5 Ω) capacitor greater than 4.7 µF (10 µF recommended, 16 V) to ground and must not be connected to VDD. |+| 18 | TMS/PWM3H/RP43/RB11 | input | JTAG test mode select input; also shared with PWM3H high output, remappable RP43 and PORTB RB11. |+| 19 | TCK/PWM3L/RP44/RB12 | input | JTAG test clock input; also shared with PWM3L low output, remappable RP44 and PORTB RB12. |+| 20 | PWM2H/RP45/RB13 | output | PWM high output 2 (generator 2), also remappable RP45 and PORTB RB13. |+| 21 | PWM2L/RP46/RB14 | output | PWM low output 2 (generator 2), also remappable RP46 and PORTB RB14. |+| 22 | PWM1H/RA4 | output | PWM high output 1 (generator 1), also PORTA RA4. |+| 23 | PWM1L/RA3 | output | PWM low output 1 (generator 1), also PORTA RA3. |+| 24 | AVSS | power_in | Ground reference for analog modules; must be connected at all times, regardless of whether the ADC is used. |+| 25 | AVDD | power_in | Positive supply for analog modules; must be connected at all times, regardless of whether the ADC is used. |+| 26 | MCLR | input | Master Clear (Reset) input; active-low Reset to the device, also used for programming and debugging. |+| 27 | AN0/PGA1P1/CMP1A/RA0 | input | Analog input AN0 (also PGA1P1, CMP1A) shared with PORTA RA0; ANSELx must be cleared before the digital function can be used. |+| 28 | AN1/PGA1P2/PGA2P1/CMP1B/RA1 | input | Analog input AN1 (also PGA1P2, PGA2P1, CMP1B) shared with PORTA RA1; ANSELx must be cleared before the digital function can be used. |+| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Microchip Tech |+| Package | QFN-28-EP(6x6) |+| Category | Embedded Processors & Controllers |+| Pins | 29 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Ambient temperature under bias | | -40 | | 125 | °C | | 303 |+| Storage temperature | | -65 | | 150 | °C | | 303 |+| Voltage on VDD with respect to VSS | | -0.3 | | 4 | V | | 303 |+| Voltage on any pin that is not 5V tolerant with respect to VSS (upper limit printed as VDD + 0.3V) | | -0.3 | | | V | | 303 |+| Voltage on any 5V tolerant pin with respect to VSS | | -0.3 | | 5.5 | V | when VDD ≥ 3.0V | 303 |+| Voltage on any 5V tolerant pin with respect to VSS | | -0.3 | | 3.6 | V | when VDD < 3.0V | 303 |+| Supply voltage | VDD | 3 | | 3.6 | V | | 305 |+| RAM retention voltage | VDR | 1.8 | | | V | -40ºC | 305 |+| RAM retention voltage | VDR | 2 | | | V | +25ºC, +85ºC, +125ºC | 305 |+| VDD rise rate to ensure internal power-on reset signal | SVDD | 1 | | | V/ms | 0V-3V in 3 ms | 305 |+| Maximum MIPS | | | | 70 | MIPS | VDD 3.0V to 3.6V; -40°C to +85°C | 304 |+| Operating junction temperature range (industrial devices) | TJ | -40 | | 125 | °C | Industrial temperature devices | 304 |+| Operating ambient temperature range (industrial devices) | TA | -40 | | 85 | °C | Industrial temperature devices | 304 |+| External filter capacitor value (CEFC) | CEFC | 4.7 | 10 | | µF | Capacitor must have a low series resistance (<1 ohm) | 305 |+| Capacitive loading on OSC2 pin | COSCO | | | 15 | pF | In XT and HS modes, when external clock is used to drive OSC1 | 315 |+| Capacitive loading on all I/O pins and OSC2 | CIO | | | 50 | pF | EC mode | 315 |+| Capacitive loading on SCLx, SDAx pins | CB | | | 400 | pF | In I2C mode | 315 |+| Package thermal resistance, 28-pin QFN-S 6x6x0.9 mm (junction to ambient) | JA | | 30 | | °C/W | Junction to ambient, from package simulations (Note 1) | 304 |++## CAD (KiCad official)++- Symbol: `dsPIC33EP16GS502-I`+- Footprint: `Package_DFN_QFN:QFN-28-1EP_6x6mm_P0.65mm_EP4.8x4.8mm`+- 3D model: QFN-28-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.5 mm tall, datasheet A, nominal). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)+- 3D model files: `dspic33ep16gs502-i-mm-etched.step` / `dspic33ep16gs502-i-mm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dspic33ep16gs502-i-mm.step` / `dspic33ep16gs502-i-mm.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Microchip Tech datasheet](docs/dspic33ep16gs502-i-mm-datasheet.pdf) (390 pp, sha256 `2372ebf6b5115c5d`, retrieved 2026-11-12, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dspic33ep16gs502-i-mm-datasheet.pdf)
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package.jsonadded+368@@ -0,0 +1,368 @@+{+ "slug": "dspic33ep16gs502-i-mm",+ "version": "0.1.0",+ "type": "component",+ "description": "Microchip Tech MICROCHIP, QFN-28-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "dspic33ep16gs502-i",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dspic33ep16gs502-i-mm.kicad_sym",+ "dspic33ep16gs502-i-mm.kicad_mod",+ "dspic33ep16gs502-i-mm.glb",+ "dspic33ep16gs502-i-mm.step",+ "dspic33ep16gs502-i-mm.lbr",+ "docs/hero.png",+ "docs/dspic33ep16gs502-i-mm-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "dspic33ep16gs502-i-mm-hero.glb",+ "dspic33ep16gs502-i-mm-hero.overlay.json"+ ],+ "component": {+ "mpn": "dsPIC33EP16GS502-I/MM",+ "manufacturer": "Microchip Tech",+ "package": "QFN-28-EP(6x6)",+ "pin_count": 29,+ "category": "Embedded Processors & Controllers",+ "subcategory": "MICROCHIP",+ "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/24e1ead09509756cc02f49a28792cdc3.pdf",+ "parts": {+ "symbol": "dspic33ep16gs502-i-mm.kicad_sym",+ "footprint": "dspic33ep16gs502-i-mm.kicad_mod",+ "model_3d": "dspic33ep16gs502-i-mm-hero.glb",+ "model_3d_plain": "dspic33ep16gs502-i-mm.glb",+ "model_3d_step": "dspic33ep16gs502-i-mm-etched.step",+ "model_3d_step_plain": "dspic33ep16gs502-i-mm.step",+ "lbr": "dspic33ep16gs502-i-mm.lbr"+ },+ "distributor_links": {+ "lcsc": "C639614",+ "digikey": "DSPIC33EP16GS502-I/MM-ND",+ "mouser": "579-33EP16GS502I/MM"+ },+ "distributor_check": {+ "checked_at": "2026-11-12T20:03:04Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "DSPIC33EP16GS502-I/MM-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "579-33EP16GS502I/MM",+ "status": "found"+ },+ "matched_as": "dsPIC33EP16GS502-I/MM"+ },+ "pins": [+ {+ "number": "1",+ "name": "AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2",+ "type": "input",+ "description": "Analog input AN2 (also PGA1P3, PGA2P2, CMP1C, CMP2A, PORTA RA2); analog functions are enabled by default after Reset and disable the digital input buffer until ANSELx is cleared."+ },+ {+ "number": "2",+ "name": "AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0",+ "type": "input",+ "description": "Analog input AN3 (also PGA2P3, CMP1D, CMP2B) shared with remappable RP32 and PORTB RB0; ANSELx must be cleared before the digital function can be used."+ },+ {+ "number": "3",+ "name": "AN4/CMP2C/CMP3A/ISRC4/RP41/RB9",+ "type": "input",+ "description": "Analog input AN4 (also CMP2C, CMP3A, constant-current output ISRC4) shared with remappable RP41 and PORTB RB9."+ },+ {+ "number": "4",+ "name": "AN5/CMP2D/CMP3B/ISRC3/RP42/RB10",+ "type": "input",+ "description": "Analog input AN5 (also CMP2D, CMP3B, constant-current output ISRC3) shared with remappable RP42 and PORTB RB10."+ },+ {+ "number": "5",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins."+ },+ {+ "number": "6",+ "name": "OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1",+ "type": "input",+ "description": "Oscillator crystal input (ST buffer in RC mode, CMOS otherwise) or external clock source input CLKI, also shared with AN6 and PORTB RB1."+ },+ {+ "number": "7",+ "name": "OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2",+ "type": "bidirectional",+ "description": "Oscillator crystal output connecting to a crystal in XT/HS mode, optionally CLKO in RC/EC modes (function selected by OSCIOFNC); also shared with AN7, PGA1N2 and PORTB RB2."+ },+ {+ "number": "8",+ "name": "PGED2/AN18/DACOUT1/INT0/RP35/RB3",+ "type": "bidirectional",+ "description": "Data I/O pin for programming/debugging communication channel 2; also shared with AN18, DACOUT1, external interrupt INT0 (not remappable) and RB3."+ },+ {+ "number": "9",+ "name": "PGEC2/ADTRG31/EXTREF1/RP36/RB4",+ "type": "input",+ "description": "Clock input pin for programming/debugging communication channel 2; also shared with external ADC trigger ADTRG31 and external reference input EXTREF1."+ },+ {+ "number": "10",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral logic and I/O pins, specified for 3.0 V to 3.6 V operation."+ },+ {+ "number": "11",+ "name": "PGED3/SDA2/FLT31/RP40/RB8",+ "type": "bidirectional",+ "description": "Data I/O pin for programming/debugging communication channel 3; also shared with I2C2 data SDA2, Class B PWM Fault input FLT31 (not remappable) and RB8."+ },+ {+ "number": "12",+ "name": "PGEC3/SCL2/RP47/RB15",+ "type": "input",+ "description": "Clock input pin for programming/debugging communication channel 3; also shared with I2C2 clock SCL2 and PORTB RB15."+ },+ {+ "number": "13",+ "name": "TDO/AN19/PGA2N2/RP37/RB5",+ "type": "output",+ "description": "JTAG test data output pin; also shared with AN19, PGA2N2 negative input and PORTB RB5."+ },+ {+ "number": "14",+ "name": "PGED1/TDI/AN20/SCL1/RP38/RB6",+ "type": "bidirectional",+ "description": "Data I/O pin for programming/debugging communication channel 1; also shared with JTAG test data input TDI, AN20, I2C1 clock SCL1 and PORTB RB6."+ },+ {+ "number": "15",+ "name": "PGEC1/AN21/SDA1/RP39/RB7",+ "type": "input",+ "description": "Clock input pin for programming/debugging communication channel 1; also shared with AN21, I2C1 data SDA1 and PORTB RB7."+ },+ {+ "number": "16",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins."+ },+ {+ "number": "17",+ "name": "VCAP",+ "type": "power_out",+ "description": "CPU logic filter capacitor connection; requires a low-ESR (<0.5 Ω) capacitor greater than 4.7 µF (10 µF recommended, 16 V) to ground and must not be connected to VDD."+ },+ {+ "number": "18",+ "name": "TMS/PWM3H/RP43/RB11",+ "type": "input",+ "description": "JTAG test mode select input; also shared with PWM3H high output, remappable RP43 and PORTB RB11."+ },+ {+ "number": "19",+ "name": "TCK/PWM3L/RP44/RB12",+ "type": "input",+ "description": "JTAG test clock input; also shared with PWM3L low output, remappable RP44 and PORTB RB12."+ },+ {+ "number": "20",+ "name": "PWM2H/RP45/RB13",+ "type": "output",+ "description": "PWM high output 2 (generator 2), also remappable RP45 and PORTB RB13."+ },+ {+ "number": "21",+ "name": "PWM2L/RP46/RB14",+ "type": "output",+ "description": "PWM low output 2 (generator 2), also remappable RP46 and PORTB RB14."+ },+ {+ "number": "22",+ "name": "PWM1H/RA4",+ "type": "output",+ "description": "PWM high output 1 (generator 1), also PORTA RA4."+ },+ {+ "number": "23",+ "name": "PWM1L/RA3",+ "type": "output",+ "description": "PWM low output 1 (generator 1), also PORTA RA3."+ },+ {+ "number": "24",+ "name": "AVSS",+ "type": "power_in",+ "description": "Ground reference for analog modules; must be connected at all times, regardless of whether the ADC is used."+ },+ {+ "number": "25",+ "name": "AVDD",+ "type": "power_in",+ "description": "Positive supply for analog modules; must be connected at all times, regardless of whether the ADC is used."+ },+ {+ "number": "26",+ "name": "MCLR",+ "type": "input",+ "description": "Master Clear (Reset) input; active-low Reset to the device, also used for programming and debugging."+ },+ {+ "number": "27",+ "name": "AN0/PGA1P1/CMP1A/RA0",+ "type": "input",+ "description": "Analog input AN0 (also PGA1P1, CMP1A) shared with PORTA RA0; ANSELx must be cleared before the digital function can be used."+ },+ {+ "number": "28",+ "name": "AN1/PGA1P2/PGA2P1/CMP1B/RA1",+ "type": "input",+ "description": "Analog input AN1 (also PGA1P2, PGA2P1, CMP1B) shared with PORTA RA1; ANSELx must be cleared before the digital function can be used."+ },+ {+ "number": "29",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed pad (EP) has no pin number in the datasheet text. The 28-lead UQFN drawing (pages 358-35; The 28-lead QFN-S (6x6x0.9 mm) package drawing is not in the supplied text (page 356 is absent). The; Pin types for multiplexed pins follow the left-most function name, as the datasheet's priority rule "+ ],+ "pages_sent": 76,+ "cost_usd": 0.3591,+ "at": "2026-11-12T20:02:47"+ },+ "datasheet": {+ "url": "https://datasheet.lcsc.com/datasheet/pdf/24e1ead09509756cc02f49a28792cdc3.pdf",+ "pages": 390,+ "sha256": "2372ebf6b5115c5d",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "model_3d_generated": {+ "generator": "factory/gen_pkg3d.py",+ "family": "QFN",+ "height_mm": 0.5,+ "height_basis": "datasheet A, nominal",+ "standoff_mm": 0.0+ },+ "pins": {+ "total": 29,+ "described": 29,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dspic33ep16gs502-i-mm.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.02,+ 6.02,+ 0.5+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "41e604cc7cbcba5a2f97f0816a5a7b5fb08f7d1d19129a298e05cb7932c5286e",+ "checked": "2026-11-12",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dspic33ep16gs502-i-mm-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.02,+ 6.02,+ 0.5+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "3c86aa03e66a0a520acb42694283db0119a4b5aa93a56dd5fd7bd68a12c5eddb",+ "checked": "2026-11-12",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ],+ "package_dims": {+ "package_code": "2N",+ "source_page": 359,+ "D": {+ "nom_mm": 6.0,+ "range_mm": [+ null,+ null+ ]+ },+ "E1": {+ "nom_mm": 6.0,+ "range_mm": [+ null,+ null+ ]+ },+ "e": {+ "nom_mm": 0.65,+ "range_mm": [+ null,+ null+ ]+ },+ "A": {+ "nom_mm": 0.5,+ "range_mm": [+ 0.45,+ 0.55+ ]+ },+ "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",+ "model_check": {+ "file": "dspic33ep16gs502-i-mm.step",+ "verdict": "PASS",+ "reasons": [+ "height within the datasheet's package drawing"+ ],+ "by": "factory/package_fit.py"+ }+ }+ }+}
page.jsonadded+373@@ -0,0 +1,373 @@+{+ "slug": "dspic33ep16gs502-i-mm",+ "version": "0.1.0",+ "type": "component",+ "description": "Microchip Tech MICROCHIP, QFN-28-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "dspic33ep16gs502-i",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dspic33ep16gs502-i-mm.kicad_sym",+ "dspic33ep16gs502-i-mm.kicad_mod",+ "dspic33ep16gs502-i-mm.glb",+ "dspic33ep16gs502-i-mm.step",+ "dspic33ep16gs502-i-mm.lbr",+ "docs/hero.png",+ "docs/dspic33ep16gs502-i-mm-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "dspic33ep16gs502-i-mm-hero.glb",+ "dspic33ep16gs502-i-mm-hero.overlay.json"+ ],+ "component": {+ "mpn": "dsPIC33EP16GS502-I/MM",+ "manufacturer": "Microchip Tech",+ "package": "QFN-28-EP(6x6)",+ "pin_count": 29,+ "category": "Embedded Processors & Controllers",+ "subcategory": "MICROCHIP",+ "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/24e1ead09509756cc02f49a28792cdc3.pdf",+ "parts": {+ "symbol": "dspic33ep16gs502-i-mm.kicad_sym",+ "footprint": "dspic33ep16gs502-i-mm.kicad_mod",+ "model_3d": "dspic33ep16gs502-i-mm-hero.glb",+ "model_3d_plain": "dspic33ep16gs502-i-mm.glb",+ "model_3d_step": "dspic33ep16gs502-i-mm-etched.step",+ "model_3d_step_plain": "dspic33ep16gs502-i-mm.step",+ "lbr": "dspic33ep16gs502-i-mm.lbr"+ },+ "distributor_links": {+ "lcsc": "C639614",+ "digikey": "DSPIC33EP16GS502-I/MM-ND",+ "mouser": "579-33EP16GS502I/MM"+ },+ "distributor_check": {+ "checked_at": "2026-11-12T20:03:04Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "DSPIC33EP16GS502-I/MM-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "579-33EP16GS502I/MM",+ "status": "found"+ },+ "matched_as": "dsPIC33EP16GS502-I/MM"+ },+ "pins": [+ {+ "number": "1",+ "name": "AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2",+ "type": "input",+ "description": "Analog input AN2 (also PGA1P3, PGA2P2, CMP1C, CMP2A, PORTA RA2); analog functions are enabled by default after Reset and disable the digital input buffer until ANSELx is cleared."+ },+ {+ "number": "2",+ "name": "AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0",+ "type": "input",+ "description": "Analog input AN3 (also PGA2P3, CMP1D, CMP2B) shared with remappable RP32 and PORTB RB0; ANSELx must be cleared before the digital function can be used."+ },+ {+ "number": "3",+ "name": "AN4/CMP2C/CMP3A/ISRC4/RP41/RB9",+ "type": "input",+ "description": "Analog input AN4 (also CMP2C, CMP3A, constant-current output ISRC4) shared with remappable RP41 and PORTB RB9."+ },+ {+ "number": "4",+ "name": "AN5/CMP2D/CMP3B/ISRC3/RP42/RB10",+ "type": "input",+ "description": "Analog input AN5 (also CMP2D, CMP3B, constant-current output ISRC3) shared with remappable RP42 and PORTB RB10."+ },+ {+ "number": "5",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins."+ },+ {+ "number": "6",+ "name": "OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1",+ "type": "input",+ "description": "Oscillator crystal input (ST buffer in RC mode, CMOS otherwise) or external clock source input CLKI, also shared with AN6 and PORTB RB1."+ },+ {+ "number": "7",+ "name": "OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2",+ "type": "bidirectional",+ "description": "Oscillator crystal output connecting to a crystal in XT/HS mode, optionally CLKO in RC/EC modes (function selected by OSCIOFNC); also shared with AN7, PGA1N2 and PORTB RB2."+ },+ {+ "number": "8",+ "name": "PGED2/AN18/DACOUT1/INT0/RP35/RB3",+ "type": "bidirectional",+ "description": "Data I/O pin for programming/debugging communication channel 2; also shared with AN18, DACOUT1, external interrupt INT0 (not remappable) and RB3."+ },+ {+ "number": "9",+ "name": "PGEC2/ADTRG31/EXTREF1/RP36/RB4",+ "type": "input",+ "description": "Clock input pin for programming/debugging communication channel 2; also shared with external ADC trigger ADTRG31 and external reference input EXTREF1."+ },+ {+ "number": "10",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral logic and I/O pins, specified for 3.0 V to 3.6 V operation."+ },+ {+ "number": "11",+ "name": "PGED3/SDA2/FLT31/RP40/RB8",+ "type": "bidirectional",+ "description": "Data I/O pin for programming/debugging communication channel 3; also shared with I2C2 data SDA2, Class B PWM Fault input FLT31 (not remappable) and RB8."+ },+ {+ "number": "12",+ "name": "PGEC3/SCL2/RP47/RB15",+ "type": "input",+ "description": "Clock input pin for programming/debugging communication channel 3; also shared with I2C2 clock SCL2 and PORTB RB15."+ },+ {+ "number": "13",+ "name": "TDO/AN19/PGA2N2/RP37/RB5",+ "type": "output",+ "description": "JTAG test data output pin; also shared with AN19, PGA2N2 negative input and PORTB RB5."+ },+ {+ "number": "14",+ "name": "PGED1/TDI/AN20/SCL1/RP38/RB6",+ "type": "bidirectional",+ "description": "Data I/O pin for programming/debugging communication channel 1; also shared with JTAG test data input TDI, AN20, I2C1 clock SCL1 and PORTB RB6."+ },+ {+ "number": "15",+ "name": "PGEC1/AN21/SDA1/RP39/RB7",+ "type": "input",+ "description": "Clock input pin for programming/debugging communication channel 1; also shared with AN21, I2C1 data SDA1 and PORTB RB7."+ },+ {+ "number": "16",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins."+ },+ {+ "number": "17",+ "name": "VCAP",+ "type": "power_out",+ "description": "CPU logic filter capacitor connection; requires a low-ESR (<0.5 Ω) capacitor greater than 4.7 µF (10 µF recommended, 16 V) to ground and must not be connected to VDD."+ },+ {+ "number": "18",+ "name": "TMS/PWM3H/RP43/RB11",+ "type": "input",+ "description": "JTAG test mode select input; also shared with PWM3H high output, remappable RP43 and PORTB RB11."+ },+ {+ "number": "19",+ "name": "TCK/PWM3L/RP44/RB12",+ "type": "input",+ "description": "JTAG test clock input; also shared with PWM3L low output, remappable RP44 and PORTB RB12."+ },+ {+ "number": "20",+ "name": "PWM2H/RP45/RB13",+ "type": "output",+ "description": "PWM high output 2 (generator 2), also remappable RP45 and PORTB RB13."+ },+ {+ "number": "21",+ "name": "PWM2L/RP46/RB14",+ "type": "output",+ "description": "PWM low output 2 (generator 2), also remappable RP46 and PORTB RB14."+ },+ {+ "number": "22",+ "name": "PWM1H/RA4",+ "type": "output",+ "description": "PWM high output 1 (generator 1), also PORTA RA4."+ },+ {+ "number": "23",+ "name": "PWM1L/RA3",+ "type": "output",+ "description": "PWM low output 1 (generator 1), also PORTA RA3."+ },+ {+ "number": "24",+ "name": "AVSS",+ "type": "power_in",+ "description": "Ground reference for analog modules; must be connected at all times, regardless of whether the ADC is used."+ },+ {+ "number": "25",+ "name": "AVDD",+ "type": "power_in",+ "description": "Positive supply for analog modules; must be connected at all times, regardless of whether the ADC is used."+ },+ {+ "number": "26",+ "name": "MCLR",+ "type": "input",+ "description": "Master Clear (Reset) input; active-low Reset to the device, also used for programming and debugging."+ },+ {+ "number": "27",+ "name": "AN0/PGA1P1/CMP1A/RA0",+ "type": "input",+ "description": "Analog input AN0 (also PGA1P1, CMP1A) shared with PORTA RA0; ANSELx must be cleared before the digital function can be used."+ },+ {+ "number": "28",+ "name": "AN1/PGA1P2/PGA2P1/CMP1B/RA1",+ "type": "input",+ "description": "Analog input AN1 (also PGA1P2, PGA2P1, CMP1B) shared with PORTA RA1; ANSELx must be cleared before the digital function can be used."+ },+ {+ "number": "29",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed pad (EP) has no pin number in the datasheet text. The 28-lead UQFN drawing (pages 358-35; The 28-lead QFN-S (6x6x0.9 mm) package drawing is not in the supplied text (page 356 is absent). The; Pin types for multiplexed pins follow the left-most function name, as the datasheet's priority rule "+ ],+ "pages_sent": 76,+ "cost_usd": 0.3591,+ "at": "2026-11-12T20:02:47"+ },+ "datasheet": {+ "url": "https://datasheet.lcsc.com/datasheet/pdf/24e1ead09509756cc02f49a28792cdc3.pdf",+ "pages": 390,+ "sha256": "2372ebf6b5115c5d",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "model_3d_generated": {+ "generator": "factory/gen_pkg3d.py",+ "family": "QFN",+ "height_mm": 0.5,+ "height_basis": "datasheet A, nominal",+ "standoff_mm": 0+ },+ "pins": {+ "total": 29,+ "described": 29,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dspic33ep16gs502-i-mm.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.02,+ 6.02,+ 0.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "41e604cc7cbcba5a2f97f0816a5a7b5fb08f7d1d19129a298e05cb7932c5286e",+ "checked": "2026-11-12",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dspic33ep16gs502-i-mm-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.02,+ 6.02,+ 0.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3c86aa03e66a0a520acb42694283db0119a4b5aa93a56dd5fd7bd68a12c5eddb",+ "checked": "2026-11-12",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ],+ "package_dims": {+ "package_code": "2N",+ "source_page": 359,+ "D": {+ "nom_mm": 6,+ "range_mm": [+ null,+ null+ ]+ },+ "E1": {+ "nom_mm": 6,+ "range_mm": [+ null,+ null+ ]+ },+ "e": {+ "nom_mm": 0.65,+ "range_mm": [+ null,+ null+ ]+ },+ "A": {+ "nom_mm": 0.5,+ "range_mm": [+ 0.45,+ 0.55+ ]+ },+ "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",+ "model_check": {+ "file": "dspic33ep16gs502-i-mm.step",+ "verdict": "PASS",+ "reasons": [+ "height within the datasheet's package drawing"+ ],+ "by": "factory/package_fit.py"+ }+ }+ },+ "visibility": "private",+ "org": "adom",+ "author": {+ "name": "Ray"+ }+}
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viewers/symbol.htmladded+1@@ -0,0 +1 @@+<!doctype html><title>dspic33ep16gs502-i-mm</title>