ds90ub960wrtdrq1

@@ -33,5 +33,421 @@   "author": {     "name": "Ray",     "email": "[email protected]"+  },+  "component": {+    "mpn": "DS90UB960WRTDRQ1",+    "manufacturer": "Texas Instruments",+    "package": "QFN-64-EP(9x9)",+    "pin_count": 65,+    "category": "Serializers, Deserializers",+    "datasheet": "https://www.ti.com/lit/ds/symlink/ds90ub960wrtdrq1.pdf",+    "parts": {+      "symbol": "ds90ub960wrtdrq1.kicad_sym",+      "footprint": "ds90ub960wrtdrq1.kicad_mod",+      "model_3d": "ds90ub960wrtdrq1-etched.glb",+      "model_3d_plain": "ds90ub960wrtdrq1.glb",+      "model_3d_step": "ds90ub960wrtdrq1-etched.step",+      "model_3d_step_plain": "ds90ub960wrtdrq1.step",+      "lbr": "ds90ub960wrtdrq1.lbr"+    },+    "pins": [+      {+        "number": "1",+        "name": "VDD18_P3",+        "type": "power_in",+        "description": "1.8-V (+-5%) power supply for FPD-Link III RX Port 3 domain. Requires 0.1/0.01-uF caps to GND per pin plus 1-uF and 10-uF bulk for the group."+      },+      {+        "number": "2",+        "name": "VDD18_P2",+        "type": "power_in",+        "description": "1.8-V (+-5%) power supply for FPD-Link III RX Port 2 domain. Requires 0.1/0.01-uF caps to GND per pin plus 1-uF and 10-uF bulk for the group."+      },+      {+        "number": "3",+        "name": "PDB",+        "type": "input",+        "description": "Active-high, inverted power-down enable. Internal 50-kOhm pulldown; must be held LOW until supplies are stable, then driven HIGH (1.8 V) to enable the device. Input is 3.3-V tolerant."+      },+      {+        "number": "4",+        "name": "RES",+        "type": "passive",+        "description": "Reserved. Must be tied to GND for normal operation."+      },+      {+        "number": "5",+        "name": "REFCLK",+        "type": "input",+        "description": "Reference-clock input; drive with a 23-26 MHz LVCMOS oscillator (100 ppm). Use 25 MHz for 400/800/1200/1600 Mbps CSI-2 data rates."+      },+      {+        "number": "6",+        "name": "INTB",+        "type": "output",+        "description": "Active-low, open-drain interrupt output driven by internal status registers. Recommend 4.7-kOhm pullup to 1.8 V or 3.3 V; leave NC if unused."+      },+      {+        "number": "7",+        "name": "I2C_SDA2",+        "type": "bidirectional",+        "description": "Secondary I2C data (open drain, up to 1 MHz Fast-Mode Plus). Recommend 2.2-4.7 kOhm pullup to 1.8 V or 3.3 V."+      },+      {+        "number": "8",+        "name": "I2C_SCL2",+        "type": "bidirectional",+        "description": "Secondary I2C clock (open drain, up to 1 MHz Fast-Mode Plus). Recommend 2.2-4.7 kOhm pullup to 1.8 V or 3.3 V."+      },+      {+        "number": "9",+        "name": "GPIO0",+        "type": "bidirectional",+        "description": "General-purpose I/O with 25-kOhm internal pulldown; disabled by default. Can mirror a remote serializer GPIO or drive locally-controlled state."+      },+      {+        "number": "10",+        "name": "GPIO1",+        "type": "bidirectional",+        "description": "General-purpose I/O with 25-kOhm internal pulldown; disabled by default."+      },+      {+        "number": "11",+        "name": "I2C_SDA",+        "type": "bidirectional",+        "description": "Primary I2C data (open drain, up to 1 MHz Fast-Mode Plus). Recommend 2.2-4.7 kOhm pullup to 1.8 V or 3.3 V."+      },+      {+        "number": "12",+        "name": "I2C_SCL",+        "type": "bidirectional",+        "description": "Primary I2C clock (open drain, up to 1 MHz Fast-Mode Plus). Recommend 2.2-4.7 kOhm pullup to 1.8 V or 3.3 V."+      },+      {+        "number": "13",+        "name": "VDDL1",+        "type": "power_in",+        "description": "1.1-V (+-5%) core-logic supply. Requires 0.1/0.01-uF caps to GND per pin plus 1-uF and 10-uF bulk for the group."+      },+      {+        "number": "14",+        "name": "GPIO2",+        "type": "bidirectional",+        "description": "General-purpose I/O with 25-kOhm internal pulldown; disabled by default."+      },+      {+        "number": "15",+        "name": "GPIO3",+        "type": "bidirectional",+        "description": "General-purpose I/O with 25-kOhm internal pulldown; disabled by default."+      },+      {+        "number": "16",+        "name": "VDDIO",+        "type": "power_in",+        "description": "LVCMOS I/O supply: 1.8 V (+-5%) or 3.3 V (+-10%). Sets the operating rail for GPIO, I2C pullups, INTB, CMLOUT, and REFCLK/RES. Requires 1-uF and 0.1/0.01-uF caps to GND."+      },+      {+        "number": "17",+        "name": "GPIO4",+        "type": "bidirectional",+        "description": "General-purpose I/O with 25-kOhm internal pulldown; disabled by default."+      },+      {+        "number": "18",+        "name": "GPIO5",+        "type": "bidirectional",+        "description": "General-purpose I/O with 25-kOhm internal pulldown; disabled by default."+      },+      {+        "number": "19",+        "name": "GPIO6",+        "type": "bidirectional",+        "description": "General-purpose I/O with 25-kOhm internal pulldown; disabled by default."+      },+      {+        "number": "20",+        "name": "GPIO7",+        "type": "bidirectional",+        "description": "General-purpose I/O with 25-kOhm internal pulldown; disabled by default."+      },+      {+        "number": "21",+        "name": "VDD_CSI0",+        "type": "power_in",+        "description": "1.1-V (+-5%) supply for the CSI-2 TX Port 0 PHY. Requires 0.1/0.01-uF caps to GND at the pin plus 1-uF and 10-uF bulk for the group."+      },+      {+        "number": "22",+        "name": "CSI0_CLKN",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 0 differential clock output (negative). Leave NC if the port is unused."+      },+      {+        "number": "23",+        "name": "CSI0_CLKP",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 0 differential clock output (positive). Leave NC if the port is unused."+      },+      {+        "number": "24",+        "name": "CSI0_D0N",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 0 differential data lane 0 (negative). Configure via CSI_PORT_SEL/CSI_CTL/CSI_CTL2 registers; leave NC if unused."+      },+      {+        "number": "25",+        "name": "CSI0_D0P",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 0 differential data lane 0 (positive). Configure via CSI_PORT_SEL/CSI_CTL/CSI_CTL2 registers."+      },+      {+        "number": "26",+        "name": "CSI0_D1N",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 0 differential data lane 1 (negative)."+      },+      {+        "number": "27",+        "name": "CSI0_D1P",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 0 differential data lane 1 (positive)."+      },+      {+        "number": "28",+        "name": "CSI0_D2N",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 0 differential data lane 2 (negative)."+      },+      {+        "number": "29",+        "name": "CSI0_D2P",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 0 differential data lane 2 (positive)."+      },+      {+        "number": "30",+        "name": "CSI0_D3N",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 0 differential data lane 3 (negative)."+      },+      {+        "number": "31",+        "name": "CSI0_D3P",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 0 differential data lane 3 (positive)."+      },+      {+        "number": "32",+        "name": "VDD18A",+        "type": "power_in",+        "description": "1.8-V (+-5%) analog/PLL supply. Requires 0.1/0.01-uF caps to GND at the pin plus 1-uF and 10-uF bulk decoupling."+      },+      {+        "number": "33",+        "name": "VDD_CSI1",+        "type": "power_in",+        "description": "1.1-V (+-5%) supply for the CSI-2 TX Port 1 PHY. Requires 0.1/0.01-uF caps to GND at the pin plus 1-uF and 10-uF bulk for the group."+      },+      {+        "number": "34",+        "name": "CSI1_CLKN",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 1 differential clock output (negative). Leave NC if the port is unused."+      },+      {+        "number": "35",+        "name": "CSI1_CLKP",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 1 differential clock output (positive). Leave NC if the port is unused."+      },+      {+        "number": "36",+        "name": "CSI1_D0N",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 1 differential data lane 0 (negative)."+      },+      {+        "number": "37",+        "name": "CSI1_D0P",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 1 differential data lane 0 (positive)."+      },+      {+        "number": "38",+        "name": "CSI1_D1N",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 1 differential data lane 1 (negative)."+      },+      {+        "number": "39",+        "name": "CSI1_D1P",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 1 differential data lane 1 (positive)."+      },+      {+        "number": "40",+        "name": "CSI1_D2N",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 1 differential data lane 2 (negative)."+      },+      {+        "number": "41",+        "name": "CSI1_D2P",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 1 differential data lane 2 (positive)."+      },+      {+        "number": "42",+        "name": "CSI1_D3N",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 1 differential data lane 3 (negative)."+      },+      {+        "number": "43",+        "name": "CSI1_D3P",+        "type": "output",+        "description": "MIPI CSI-2 TX Port 1 differential data lane 3 (positive)."+      },+      {+        "number": "44",+        "name": "VDDL2",+        "type": "power_in",+        "description": "1.1-V (+-5%) core-logic supply. Requires 0.1/0.01-uF caps to GND per pin plus 1-uF and 10-uF bulk for the group."+      },+      {+        "number": "45",+        "name": "MODE",+        "type": "input",+        "description": "Mode-select strap. Set with an external pullup to VDD18 and pulldown to GND forming a voltage divider (see datasheet Table 2). Internal pulldown per IOZ spec."+      },+      {+        "number": "46",+        "name": "IDX",+        "type": "input",+        "description": "I2C device-ID address-select strap. Set with an external pullup to VDD18 and pulldown to GND forming a voltage divider (see datasheet Table 18). Internal pulldown per IOZ spec."+      },+      {+        "number": "47",+        "name": "VDD18_P1",+        "type": "power_in",+        "description": "1.8-V (+-5%) power supply for FPD-Link III RX Port 1 domain. Requires 0.1/0.01-uF caps to GND per pin plus 1-uF and 10-uF bulk for the group."+      },+      {+        "number": "48",+        "name": "VDD18_P0",+        "type": "power_in",+        "description": "1.8-V (+-5%) power supply for FPD-Link III RX Port 0 domain. Requires 0.1/0.01-uF caps to GND per pin plus 1-uF and 10-uF bulk for the group."+      },+      {+        "number": "49",+        "name": "VDD18_FPD0",+        "type": "power_in",+        "description": "1.8-V (+-5%) supply for FPD-Link III RX Port 0 analog block. Requires 0.1/0.01-uF caps at the pin plus 1-uF and 10-uF bulk for the group."+      },+      {+        "number": "50",+        "name": "RIN0+",+        "type": "bidirectional",+        "description": "FPD-Link III RX Port 0 positive line. Receives high-speed forward-channel video/control and transmits back-channel control; interfaces to a compatible serializer over 50-Ohm coax or 100-Ohm STP, AC-coupled. Disable via RX_PORT_CTL bit 0 and leave NC if unused."+      },+      {+        "number": "51",+        "name": "RIN0-",+        "type": "bidirectional",+        "description": "FPD-Link III RX Port 0 negative line. Pairs with RIN0+ for the AC-coupled differential FPD-Link III interface."+      },+      {+        "number": "52",+        "name": "VDD_FPD1",+        "type": "power_in",+        "description": "1.1-V (+-5%) supply for the FPD-Link III RX PHY (Port 1 group). Requires 0.1/0.01-uF caps at the pin plus 1-uF and 10-uF bulk for the group."+      },+      {+        "number": "53",+        "name": "RIN1+",+        "type": "bidirectional",+        "description": "FPD-Link III RX Port 1 positive line. AC-coupled differential interface to a compatible serializer over 50-Ohm coax or 100-Ohm STP. Disable via RX_PORT_CTL bit 1 and leave NC if unused."+      },+      {+        "number": "54",+        "name": "RIN1-",+        "type": "bidirectional",+        "description": "FPD-Link III RX Port 1 negative line."+      },+      {+        "number": "55",+        "name": "VDD18_FPD1",+        "type": "power_in",+        "description": "1.8-V (+-5%) supply for FPD-Link III RX Port 1 analog block. Requires 0.1/0.01-uF caps at the pin plus 1-uF and 10-uF bulk for the group."+      },+      {+        "number": "56",+        "name": "CMLOUTP",+        "type": "output",+        "description": "Channel-monitor loop-through driver differential output (positive). Route to a test point with a 100-Ohm inter-pin termination for eye/channel monitoring; leave NC if unused."+      },+      {+        "number": "57",+        "name": "CMLOUTN",+        "type": "output",+        "description": "Channel-monitor loop-through driver differential output (negative). Pairs with CMLOUTP."+      },+      {+        "number": "58",+        "name": "VDD18_FPD2",+        "type": "power_in",+        "description": "1.8-V (+-5%) supply for FPD-Link III RX Port 2 analog block. Requires 0.1/0.01-uF caps at the pin plus 1-uF and 10-uF bulk for the group."+      },+      {+        "number": "59",+        "name": "RIN2+",+        "type": "bidirectional",+        "description": "FPD-Link III RX Port 2 positive line. AC-coupled differential interface to a compatible serializer over 50-Ohm coax or 100-Ohm STP. Disable via RX_PORT_CTL bit 2 and leave NC if unused."+      },+      {+        "number": "60",+        "name": "RIN2-",+        "type": "bidirectional",+        "description": "FPD-Link III RX Port 2 negative line."+      },+      {+        "number": "61",+        "name": "VDD_FPD2",+        "type": "power_in",+        "description": "1.1-V (+-5%) supply for the FPD-Link III RX PHY (Port 2/3 group). Requires 0.1/0.01-uF caps at the pin plus 1-uF and 10-uF bulk for the group."+      },+      {+        "number": "62",+        "name": "RIN3+",+        "type": "bidirectional",+        "description": "FPD-Link III RX Port 3 positive line. AC-coupled differential interface to a compatible serializer over 50-Ohm coax or 100-Ohm STP. Disable via RX_PORT_CTL bit 3 and leave NC if unused."+      },+      {+        "number": "63",+        "name": "RIN3-",+        "type": "bidirectional",+        "description": "FPD-Link III RX Port 3 negative line."+      },+      {+        "number": "64",+        "name": "VDD18_FPD3",+        "type": "power_in",+        "description": "1.8-V (+-5%) supply for FPD-Link III RX Port 3 analog block. Requires 0.1/0.01-uF caps at the pin plus 1-uF and 10-uF bulk for the group."+      },+      {+        "number": "65",+        "name": "GND",+        "type": "power_in",+        "description": "Exposed die-attach pad (DAP) on the bottom of the VQFN package. Connect to the PCB ground plane; provides the sole ground return and primary thermal path for the device."+      }+    ],+    "provenance": {+      "rebuilt": "component block rebuilt 2026-10-05 from this page's own README pinout table and .kicad_sym (pins cross-checked), no re-extraction"+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }   }-}\ No newline at end of file+}