ds90ub960wrtdrq1

@@ -0,0 +1,106 @@+# DS90UB960WRTDRQ1++**Texas Instruments** · Serializers, Deserializers · QFN-64-EP(9x9)++DS90UB960WRTDRQ1 from Texas Instruments, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VDD18_P3 | power_in | 1.8-V (+-5%) power supply for FPD-Link III RX Port 3 domain. Requires 0.1/0.01-uF caps to GND per pin plus 1-uF and 10-uF bulk for the group. |+| 2 | VDD18_P2 | power_in | 1.8-V (+-5%) power supply for FPD-Link III RX Port 2 domain. Requires 0.1/0.01-uF caps to GND per pin plus 1-uF and 10-uF bulk for the group. |+| 3 | PDB | input | Active-high, inverted power-down enable. Internal 50-kOhm pulldown; must be held LOW until supplies are stable, then driven HIGH (1.8 V) to enable the device. Input is 3.3-V tolerant. |+| 4 | RES | passive | Reserved. Must be tied to GND for normal operation. |+| 5 | REFCLK | input | Reference-clock input; drive with a 23-26 MHz LVCMOS oscillator (100 ppm). Use 25 MHz for 400/800/1200/1600 Mbps CSI-2 data rates. |+| 6 | INTB | output | Active-low, open-drain interrupt output driven by internal status registers. Recommend 4.7-kOhm pullup to 1.8 V or 3.3 V; leave NC if unused. |+| 7 | I2C_SDA2 | bidirectional | Secondary I2C data (open drain, up to 1 MHz Fast-Mode Plus). Recommend 2.2-4.7 kOhm pullup to 1.8 V or 3.3 V. |+| 8 | I2C_SCL2 | bidirectional | Secondary I2C clock (open drain, up to 1 MHz Fast-Mode Plus). Recommend 2.2-4.7 kOhm pullup to 1.8 V or 3.3 V. |+| 9 | GPIO0 | bidirectional | General-purpose I/O with 25-kOhm internal pulldown; disabled by default. Can mirror a remote serializer GPIO or drive locally-controlled state. |+| 10 | GPIO1 | bidirectional | General-purpose I/O with 25-kOhm internal pulldown; disabled by default. |+| 11 | I2C_SDA | bidirectional | Primary I2C data (open drain, up to 1 MHz Fast-Mode Plus). Recommend 2.2-4.7 kOhm pullup to 1.8 V or 3.3 V. |+| 12 | I2C_SCL | bidirectional | Primary I2C clock (open drain, up to 1 MHz Fast-Mode Plus). Recommend 2.2-4.7 kOhm pullup to 1.8 V or 3.3 V. |+| 13 | VDDL1 | power_in | 1.1-V (+-5%) core-logic supply. Requires 0.1/0.01-uF caps to GND per pin plus 1-uF and 10-uF bulk for the group. |+| 14 | GPIO2 | bidirectional | General-purpose I/O with 25-kOhm internal pulldown; disabled by default. |+| 15 | GPIO3 | bidirectional | General-purpose I/O with 25-kOhm internal pulldown; disabled by default. |+| 16 | VDDIO | power_in | LVCMOS I/O supply: 1.8 V (+-5%) or 3.3 V (+-10%). Sets the operating rail for GPIO, I2C pullups, INTB, CMLOUT, and REFCLK/RES. Requires 1-uF and 0.1/0.01-uF caps to GND. |+| 17 | GPIO4 | bidirectional | General-purpose I/O with 25-kOhm internal pulldown; disabled by default. |+| 18 | GPIO5 | bidirectional | General-purpose I/O with 25-kOhm internal pulldown; disabled by default. |+| 19 | GPIO6 | bidirectional | General-purpose I/O with 25-kOhm internal pulldown; disabled by default. |+| 20 | GPIO7 | bidirectional | General-purpose I/O with 25-kOhm internal pulldown; disabled by default. |+| 21 | VDD_CSI0 | power_in | 1.1-V (+-5%) supply for the CSI-2 TX Port 0 PHY. Requires 0.1/0.01-uF caps to GND at the pin plus 1-uF and 10-uF bulk for the group. |+| 22 | CSI0_CLKN | output | MIPI CSI-2 TX Port 0 differential clock output (negative). Leave NC if the port is unused. |+| 23 | CSI0_CLKP | output | MIPI CSI-2 TX Port 0 differential clock output (positive). Leave NC if the port is unused. |+| 24 | CSI0_D0N | output | MIPI CSI-2 TX Port 0 differential data lane 0 (negative). Configure via CSI_PORT_SEL/CSI_CTL/CSI_CTL2 registers; leave NC if unused. |+| 25 | CSI0_D0P | output | MIPI CSI-2 TX Port 0 differential data lane 0 (positive). Configure via CSI_PORT_SEL/CSI_CTL/CSI_CTL2 registers. |+| 26 | CSI0_D1N | output | MIPI CSI-2 TX Port 0 differential data lane 1 (negative). |+| 27 | CSI0_D1P | output | MIPI CSI-2 TX Port 0 differential data lane 1 (positive). |+| 28 | CSI0_D2N | output | MIPI CSI-2 TX Port 0 differential data lane 2 (negative). |+| 29 | CSI0_D2P | output | MIPI CSI-2 TX Port 0 differential data lane 2 (positive). |+| 30 | CSI0_D3N | output | MIPI CSI-2 TX Port 0 differential data lane 3 (negative). |+| 31 | CSI0_D3P | output | MIPI CSI-2 TX Port 0 differential data lane 3 (positive). |+| 32 | VDD18A | power_in | 1.8-V (+-5%) analog/PLL supply. Requires 0.1/0.01-uF caps to GND at the pin plus 1-uF and 10-uF bulk decoupling. |+| 33 | VDD_CSI1 | power_in | 1.1-V (+-5%) supply for the CSI-2 TX Port 1 PHY. Requires 0.1/0.01-uF caps to GND at the pin plus 1-uF and 10-uF bulk for the group. |+| 34 | CSI1_CLKN | output | MIPI CSI-2 TX Port 1 differential clock output (negative). Leave NC if the port is unused. |+| 35 | CSI1_CLKP | output | MIPI CSI-2 TX Port 1 differential clock output (positive). Leave NC if the port is unused. |+| 36 | CSI1_D0N | output | MIPI CSI-2 TX Port 1 differential data lane 0 (negative). |+| 37 | CSI1_D0P | output | MIPI CSI-2 TX Port 1 differential data lane 0 (positive). |+| 38 | CSI1_D1N | output | MIPI CSI-2 TX Port 1 differential data lane 1 (negative). |+| 39 | CSI1_D1P | output | MIPI CSI-2 TX Port 1 differential data lane 1 (positive). |+| 40 | CSI1_D2N | output | MIPI CSI-2 TX Port 1 differential data lane 2 (negative). |+| 41 | CSI1_D2P | output | MIPI CSI-2 TX Port 1 differential data lane 2 (positive). |+| 42 | CSI1_D3N | output | MIPI CSI-2 TX Port 1 differential data lane 3 (negative). |+| 43 | CSI1_D3P | output | MIPI CSI-2 TX Port 1 differential data lane 3 (positive). |+| 44 | VDDL2 | power_in | 1.1-V (+-5%) core-logic supply. Requires 0.1/0.01-uF caps to GND per pin plus 1-uF and 10-uF bulk for the group. |+| 45 | MODE | input | Mode-select strap. Set with an external pullup to VDD18 and pulldown to GND forming a voltage divider (see datasheet Table 2). Internal pulldown per IOZ spec. |+| 46 | IDX | input | I2C device-ID address-select strap. Set with an external pullup to VDD18 and pulldown to GND forming a voltage divider (see datasheet Table 18). Internal pulldown per IOZ spec. |+| 47 | VDD18_P1 | power_in | 1.8-V (+-5%) power supply for FPD-Link III RX Port 1 domain. Requires 0.1/0.01-uF caps to GND per pin plus 1-uF and 10-uF bulk for the group. |+| 48 | VDD18_P0 | power_in | 1.8-V (+-5%) power supply for FPD-Link III RX Port 0 domain. Requires 0.1/0.01-uF caps to GND per pin plus 1-uF and 10-uF bulk for the group. |+| 49 | VDD18_FPD0 | power_in | 1.8-V (+-5%) supply for FPD-Link III RX Port 0 analog block. Requires 0.1/0.01-uF caps at the pin plus 1-uF and 10-uF bulk for the group. |+| 50 | RIN0+ | bidirectional | FPD-Link III RX Port 0 positive line. Receives high-speed forward-channel video/control and transmits back-channel control; interfaces to a compatible serializer over 50-Ohm coax or 100-Ohm STP, AC-coupled. Disable via RX_PORT_CTL bit 0 and leave NC if unused. |+| 51 | RIN0- | bidirectional | FPD-Link III RX Port 0 negative line. Pairs with RIN0+ for the AC-coupled differential FPD-Link III interface. |+| 52 | VDD_FPD1 | power_in | 1.1-V (+-5%) supply for the FPD-Link III RX PHY (Port 1 group). Requires 0.1/0.01-uF caps at the pin plus 1-uF and 10-uF bulk for the group. |+| 53 | RIN1+ | bidirectional | FPD-Link III RX Port 1 positive line. AC-coupled differential interface to a compatible serializer over 50-Ohm coax or 100-Ohm STP. Disable via RX_PORT_CTL bit 1 and leave NC if unused. |+| 54 | RIN1- | bidirectional | FPD-Link III RX Port 1 negative line. |+| 55 | VDD18_FPD1 | power_in | 1.8-V (+-5%) supply for FPD-Link III RX Port 1 analog block. Requires 0.1/0.01-uF caps at the pin plus 1-uF and 10-uF bulk for the group. |+| 56 | CMLOUTP | output | Channel-monitor loop-through driver differential output (positive). Route to a test point with a 100-Ohm inter-pin termination for eye/channel monitoring; leave NC if unused. |+| 57 | CMLOUTN | output | Channel-monitor loop-through driver differential output (negative). Pairs with CMLOUTP. |+| 58 | VDD18_FPD2 | power_in | 1.8-V (+-5%) supply for FPD-Link III RX Port 2 analog block. Requires 0.1/0.01-uF caps at the pin plus 1-uF and 10-uF bulk for the group. |+| 59 | RIN2+ | bidirectional | FPD-Link III RX Port 2 positive line. AC-coupled differential interface to a compatible serializer over 50-Ohm coax or 100-Ohm STP. Disable via RX_PORT_CTL bit 2 and leave NC if unused. |+| 60 | RIN2- | bidirectional | FPD-Link III RX Port 2 negative line. |+| 61 | VDD_FPD2 | power_in | 1.1-V (+-5%) supply for the FPD-Link III RX PHY (Port 2/3 group). Requires 0.1/0.01-uF caps at the pin plus 1-uF and 10-uF bulk for the group. |+| 62 | RIN3+ | bidirectional | FPD-Link III RX Port 3 positive line. AC-coupled differential interface to a compatible serializer over 50-Ohm coax or 100-Ohm STP. Disable via RX_PORT_CTL bit 3 and leave NC if unused. |+| 63 | RIN3- | bidirectional | FPD-Link III RX Port 3 negative line. |+| 64 | VDD18_FPD3 | power_in | 1.8-V (+-5%) supply for FPD-Link III RX Port 3 analog block. Requires 0.1/0.01-uF caps at the pin plus 1-uF and 10-uF bulk for the group. |+| 65 | GND | power_in | Exposed die-attach pad (DAP) on the bottom of the VQFN package. Connect to the PCB ground plane; provides the sole ground return and primary thermal path for the device. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | QFN-64-EP(9x9) |+| Category | Interface |+| Pins | 65 |++## Ordering variants++- `DS90UB960WRTDRQ1`+- `DS90UB960WRTDRQ1WRTDTQ1`++## CAD (KiCad official)++- Symbol: `DS90UB960WRTDRQ1`+- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`+- 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ds90ub960wrtdrq1.pdf) (None pp, sha256 `c1099feae7d731a7`, retrieved 2026-08-17, tier: manufacturer)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ds90ub960wrtdrq1-datasheet.pdf)