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DS90UB953TRHBRQ1
Public Made by Adomby adom
Texas Instruments Interface - Specialized, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+70@@ -0,0 +1,70 @@+# DS90UB953TRHBRQ1++**Texas Instruments** · Interface - Specialized · QFN-32-EP(5x5)++DS90UB953TRHBRQ1 from Texas Instruments, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CSI_D1P | input | CSI-2 data lane 1 positive differential input with matched 100Ω (±5%) impedance; optional, can be left floating if unused. |+| 2 | CSI_D1N | input | CSI-2 data lane 1 negative differential input with matched 100Ω (±5%) impedance; optional, can be left floating if unused. |+| 3 | CSI_D0P | input | CSI-2 data lane 0 positive differential input with matched 100Ω (±5%) impedance; optional, can be left floating if unused. |+| 4 | CSI_D0N | input | CSI-2 data lane 0 negative differential input with matched 100Ω (±5%) impedance; optional, can be left floating if unused. |+| 5 | CSI_CLKP | input | CSI-2 clock positive differential input with matched 100Ω (±5%) impedance. |+| 6 | CSI_CLKN | input | CSI-2 clock negative differential input with matched 100Ω (±5%) impedance. |+| 7 | RES0 | input | Reserved pin-must be connected to ground (GND). |+| 8 | PDB | input | Power-down bar input with internal 1MΩ pull-down; device enabled when high (1.8V), disabled when low (0V); minimum pulse width 3ms for reset. |+| 9 | LPF1 | passive | Loop filter connection for PLL; typically connected to 0.022µF capacitor between this pin and VDDPLL. |+| 10 | VDDPLL_CAP | passive | Internal PLL regulator decoupling capacitor connection; typically connected to 10µF, 0.1µF, and 0.01µF capacitors to ground. |+| 11 | VDDPLL | power_in | 1.8V ±5% analog power supply for PLL; typically connected to 1µF and 0.01µF decoupling capacitors to ground. |+| 12 | LPF2 | passive | Loop filter connection for PLL; typically connected to 0.1µF capacitor between this pin and ground. |+| 13 | DOUT- | bidirectional | FPD-Link III differential output negative line; must be AC-coupled with 15-47nF capacitor to deserializer; 50Ω characteristic impedance required. |+| 14 | DOUT+ | bidirectional | FPD-Link III differential output positive line; must be AC-coupled with 33-100nF capacitor to deserializer; 50Ω characteristic impedance required. |+| 15 | VDDDRV_CAP | passive | Internal driver regulator decoupling capacitor connection; typically connected to 10µF, 0.1µF, and 0.01µF capacitors to ground. |+| 16 | VDDDRV | power_in | 1.8V ±5% analog power supply for driver circuits; typically connected to 1µF and 0.01µF decoupling capacitors to ground. |+| 17 | GPIO_0 | bidirectional | General-purpose input/output pin with 300kΩ internal pull-down; defaults to input on power-up; can be configured to detect external voltage with 3-bit ADC. |+| 18 | GPIO_1 | bidirectional | General-purpose input/output pin with 300kΩ internal pull-down; defaults to input on power-up; can be configured to detect external voltage with 3-bit ADC. |+| 19 | CLK_OUT/IDX | bidirectional | Dual-function pin: strapped at power-up as IDX to set I2C address and pull-up voltage (1.8V or 3.3V); switches to CLK_OUT after boot with minimum 35kΩ load impedance required. |+| 20 | CLKIN | input | Reference clock input for non-synchronous external clock mode with frequency range 25-104MHz; can be left open if using synchronous mode. |+| 21 | MODE | input | Mode selection strapping pin for synchronous/asynchronous/DVP modes; voltage level at power-up determines operating mode via voltage divider to VDD18/GND. |+| 22 | RES1 | unconnected | Reserved pin-must be left unconnected (floating); do not connect to any signal or ground. |+| 23 | I2C_SDA | tri_state | I2C serial data line with open-drain output; requires external pull-up resistor to 1.8V or 3.3V as determined by IDX pin configuration. |+| 24 | I2C_SCL | tri_state | I2C serial clock line with open-drain output; requires external pull-up resistor to 1.8V or 3.3V as determined by IDX pin configuration. |+| 25 | VDDD | power_in | 1.8V ±5% digital power supply; typically connected to 1µF and 0.01µF decoupling capacitors to ground. |+| 26 | VDDD_CAP | passive | Internal digital regulator decoupling capacitor connection; typically connected to 10µF, 0.1µF, and 0.01µF capacitors to ground. |+| 27 | GPIO_2 | bidirectional | General-purpose input/output pin with 300kΩ internal pull-down; defaults to input on power-up; can be configured to detect external voltage with 3-bit ADC. |+| 28 | GPIO_3 | bidirectional | General-purpose input/output pin with 300kΩ internal pull-down; defaults to input on power-up; can be configured to detect external voltage with 3-bit ADC. |+| 29 | CSI_D3P | input | CSI-2 data lane 3 positive differential input with matched 100Ω (±5%) impedance. |+| 30 | CSI_D3N | input | CSI-2 data lane 3 negative differential input with matched 100Ω (±5%) impedance. |+| 31 | CSI_D2P | input | CSI-2 data lane 2 positive differential input with matched 100Ω (±5%) impedance. |+| 32 | CSI_D2N | input | CSI-2 data lane 2 negative differential input with matched 100Ω (±5%) impedance. |+| 33 | GND | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | QFN-32-EP(5x5) |+| Category | Interface |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `DS90UB953TRHBRQ1`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `ds90ub953trhbrq1-etched.step` / `ds90ub953trhbrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds90ub953trhbrq1.step` / `ds90ub953trhbrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds90ub953-q1) (96 pp, sha256 `a51f0cf0e165024f`, retrieved 2026-09-25, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ds90ub953trhbrq1-datasheet.pdf)
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optional, can be left floating if unused."+ },+ {+ "number": "2",+ "name": "CSI_D1N",+ "type": "input",+ "description": "CSI-2 data lane 1 negative differential input with matched 100Ω (±5%) impedance; optional, can be left floating if unused."+ },+ {+ "number": "3",+ "name": "CSI_D0P",+ "type": "input",+ "description": "CSI-2 data lane 0 positive differential input with matched 100Ω (±5%) impedance; optional, can be left floating if unused."+ },+ {+ "number": "4",+ "name": "CSI_D0N",+ "type": "input",+ "description": "CSI-2 data lane 0 negative differential input with matched 100Ω (±5%) impedance; optional, can be left floating if unused."+ },+ {+ "number": "5",+ "name": "CSI_CLKP",+ "type": "input",+ "description": "CSI-2 clock positive differential input with matched 100Ω (±5%) impedance."+ },+ {+ "number": "6",+ "name": "CSI_CLKN",+ "type": "input",+ "description": "CSI-2 clock negative differential input with matched 100Ω (±5%) impedance."+ },+ {+ "number": "7",+ "name": "RES0",+ "type": "input",+ "description": "Reserved pin-must be connected to ground (GND)."+ },+ {+ "number": "8",+ "name": "PDB",+ "type": "input",+ "description": "Power-down bar input with internal 1MΩ pull-down; device enabled when high (1.8V), disabled when low (0V); minimum pulse width 3ms for reset."+ },+ {+ "number": "9",+ "name": "LPF1",+ "type": "passive",+ "description": "Loop filter connection for PLL; typically connected to 0.022µF capacitor between this pin and VDDPLL."+ },+ {+ "number": "10",+ "name": "VDDPLL_CAP",+ "type": "passive",+ "description": "Internal PLL regulator decoupling capacitor connection; typically connected to 10µF, 0.1µF, and 0.01µF capacitors to ground."+ },+ {+ "number": "11",+ "name": "VDDPLL",+ "type": "power_in",+ "description": "1.8V ±5% analog power supply for PLL; typically connected to 1µF and 0.01µF decoupling capacitors to ground."+ },+ {+ "number": "12",+ "name": "LPF2",+ "type": "passive",+ "description": "Loop filter connection for PLL; typically connected to 0.1µF capacitor between this pin and ground."+ },+ {+ "number": "13",+ "name": "DOUT-",+ "type": "bidirectional",+ "description": "FPD-Link III differential output negative line; must be AC-coupled with 15-47nF capacitor to deserializer; 50Ω characteristic impedance required."+ },+ {+ "number": "14",+ "name": "DOUT+",+ "type": "bidirectional",+ "description": "FPD-Link III differential output positive line; must be AC-coupled with 33-100nF capacitor to deserializer; 50Ω characteristic impedance required."+ },+ {+ "number": "15",+ "name": "VDDDRV_CAP",+ "type": "passive",+ "description": "Internal driver regulator decoupling capacitor connection; typically connected to 10µF, 0.1µF, and 0.01µF capacitors to ground."+ },+ {+ "number": "16",+ "name": "VDDDRV",+ "type": "power_in",+ "description": "1.8V ±5% analog power supply for driver circuits; typically connected to 1µF and 0.01µF decoupling capacitors to ground."+ },+ {+ "number": "17",+ "name": "GPIO_0",+ "type": "bidirectional",+ "description": "General-purpose input/output pin with 300kΩ internal pull-down; defaults to input on power-up; can be configured to detect external voltage with 3-bit ADC."+ },+ {+ "number": "18",+ "name": "GPIO_1",+ "type": "bidirectional",+ "description": "General-purpose input/output pin with 300kΩ internal pull-down; defaults to input on power-up; can be configured to detect external voltage with 3-bit ADC."+ },+ {+ "number": "19",+ "name": "CLK_OUT/IDX",+ "type": "bidirectional",+ "description": "Dual-function pin: strapped at power-up as IDX to set I2C address and pull-up voltage (1.8V or 3.3V); switches to CLK_OUT after boot with minimum 35kΩ load impedance required."+ },+ {+ "number": "20",+ "name": "CLKIN",+ "type": "input",+ "description": "Reference clock input for non-synchronous external clock mode with frequency range 25-104MHz; can be left open if using synchronous mode."+ },+ {+ "number": "21",+ "name": "MODE",+ "type": "input",+ "description": "Mode selection strapping pin for synchronous/asynchronous/DVP modes; voltage level at power-up determines operating mode via voltage divider to VDD18/GND."+ },+ {+ "number": "22",+ "name": "RES1",+ "type": "unconnected",+ "description": "Reserved pin-must be left unconnected (floating); do not connect to any signal or ground."+ },+ {+ "number": "23",+ "name": "I2C_SDA",+ "type": "tri_state",+ "description": "I2C serial data line with open-drain output; requires external pull-up resistor to 1.8V or 3.3V as determined by IDX pin configuration."+ },+ {+ "number": "24",+ "name": "I2C_SCL",+ "type": "tri_state",+ "description": "I2C serial clock line with open-drain output; requires external pull-up resistor to 1.8V or 3.3V as determined by IDX pin configuration."+ },+ {+ "number": "25",+ "name": "VDDD",+ "type": "power_in",+ "description": "1.8V ±5% digital power supply; typically connected to 1µF and 0.01µF decoupling capacitors to ground."+ },+ {+ "number": "26",+ "name": "VDDD_CAP",+ "type": "passive",+ "description": "Internal digital regulator decoupling capacitor connection; typically connected to 10µF, 0.1µF, and 0.01µF capacitors to ground."+ },+ {+ "number": "27",+ "name": "GPIO_2",+ "type": "bidirectional",+ "description": "General-purpose input/output pin with 300kΩ internal pull-down; defaults to input on power-up; can be configured to detect external voltage with 3-bit ADC."+ },+ {+ "number": "28",+ "name": "GPIO_3",+ "type": "bidirectional",+ "description": "General-purpose input/output pin with 300kΩ internal pull-down; defaults to input on power-up; can be configured to detect external voltage with 3-bit ADC."+ },+ {+ "number": "29",+ "name": "CSI_D3P",+ "type": "input",+ "description": "CSI-2 data lane 3 positive differential input with matched 100Ω (±5%) impedance."+ },+ {+ "number": "30",+ "name": "CSI_D3N",+ "type": "input",+ "description": "CSI-2 data lane 3 negative differential input with matched 100Ω (±5%) impedance."+ },+ {+ "number": "31",+ "name": "CSI_D2P",+ "type": "input",+ "description": "CSI-2 data lane 2 positive differential input with matched 100Ω (±5%) impedance."+ },+ {+ "number": "32",+ "name": "CSI_D2N",+ "type": "input",+ "description": "CSI-2 data lane 2 negative differential input with matched 100Ω (±5%) impedance."+ },+ {+ "number": "33",+ "name": "GND",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 33 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 96,+ "cost_usd": 1.2876,+ "at": "2026-09-25T14:18:21"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ds90ub953-q1",+ "pages": 96,+ "sha256": "a51f0cf0e165024f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}