component
DS90UB936TRGZRQ1
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Texas Instruments LVDS ICs, VQFN-48-EP(7x7). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+372−8@@ -1,13 +1,382 @@ {+ "schema_version": 1,+ "type": "component", "slug": "ds90ub936trgzrq1",+ "title": "DS90UB936TRGZRQ1",+ "brief": "Texas Instruments LVDS ICs, VQFN-48-EP(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Texas Instruments LVDS ICs, VQFN-48-EP(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "interface", "ds90ub936trgzrq1" ],+ "component": {+ "mpn": "DS90UB936TRGZRQ1",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-48-EP(7x7)",+ "pin_count": 49,+ "category": "Interface",+ "subcategory": "LVDS ICs",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ds90ub936-q1",+ "parts": {+ "symbol": "ds90ub936trgzrq1.kicad_sym",+ "footprint": "ds90ub936trgzrq1.kicad_mod",+ "model_3d": "ds90ub936trgzrq1.glb",+ "model_3d_step": "ds90ub936trgzrq1.step",+ "lbr": "ds90ub936trgzrq1.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "I2C_SDA",+ "type": "bidirectional",+ "description": "I2C serial data line for bidirectional control-bus communication. Open-drain, 3.3-V tolerant. External 2 k\u03a9-4.7 k\u03a9 pull-up to 1.8 V or 3.3 V required."+ },+ {+ "number": "2",+ "name": "I2C_SCL",+ "type": "bidirectional",+ "description": "I2C serial clock line for bidirectional control-bus communication. Open-drain, 3.3-V tolerant. External 2 k\u03a9-4.7 k\u03a9 pull-up to 1.8 V or 3.3 V required."+ },+ {+ "number": "3",+ "name": "VDD11_D",+ "type": "power_in",+ "description": "1.1 V core-digital supply / internal-regulator decoupling. If VDD_SEL=LOW, do not tie to a 1.1-V rail (internal LDO drives); requires 0.01-0.1 \u00b5F and 4.7 \u00b5F caps to GND. If VDD_SEL=HIGH, connect to external 1.1 V \u00b15%."+ },+ {+ "number": "4",+ "name": "XOUT",+ "type": "output",+ "description": "Crystal oscillator output. Drive a 23-26 MHz crystal across XIN/XOUT, or leave NC when an external reference clock drives XIN/REFCLK."+ },+ {+ "number": "5",+ "name": "XIN/REFCLK",+ "type": "input",+ "description": "Reference-clock input or crystal-oscillator input. Accepts a 23-26 MHz reference (100 ppm) or one leg of a 23-26 MHz crystal to XOUT."+ },+ {+ "number": "6",+ "name": "BISTEN",+ "type": "input",+ "description": "Built-in self-test enable. H = BIST enabled, L = disabled. Internal pull-down; tie directly to GND if unused."+ },+ {+ "number": "7",+ "name": "VDDIO",+ "type": "power_in",+ "description": "LVCMOS I/O supply: 1.8 V or 3.3 V. When at 1.8 V, must track V(VDD18) within \u00b1100 mV. Requires 1 \u00b5F + 0.01 \u00b5F cap to GND per VDDIO pin."+ },+ {+ "number": "8",+ "name": "GPIO6",+ "type": "bidirectional",+ "description": "General-purpose I/O. Configurable to mirror a serializer GPIO or follow local register settings. Powered from VDDIO. Internal 35 k\u03a9 pull-down; disabled at power-up."+ },+ {+ "number": "9",+ "name": "GPIO5",+ "type": "bidirectional",+ "description": "General-purpose I/O. Configurable to mirror a serializer GPIO or follow local register settings. Powered from VDDIO. Internal 35 k\u03a9 pull-down; disabled at power-up."+ },+ {+ "number": "10",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General-purpose I/O. Configurable to mirror a serializer GPIO or follow local register settings. Powered from VDDIO. Internal 35 k\u03a9 pull-down; disabled at power-up."+ },+ {+ "number": "11",+ "name": "CSI_CLK0N",+ "type": "output",+ "description": "MIPI CSI-2 differential clock lane 0, negative. DPHY output from FPD-Link III deserializer to host SoC."+ },+ {+ "number": "12",+ "name": "CSI_CLK0P",+ "type": "output",+ "description": "MIPI CSI-2 differential clock lane 0, positive. DPHY output from FPD-Link III deserializer to host SoC."+ },+ {+ "number": "13",+ "name": "CSI_D0N",+ "type": "output",+ "description": "MIPI CSI-2 differential data lane 0, negative. Up to 1.664 Gbps per lane. Leave NC if unused."+ },+ {+ "number": "14",+ "name": "CSI_D0P",+ "type": "output",+ "description": "MIPI CSI-2 differential data lane 0, positive. Up to 1.664 Gbps per lane. Leave NC if unused."+ },+ {+ "number": "15",+ "name": "CSI_D1N",+ "type": "output",+ "description": "MIPI CSI-2 differential data lane 1, negative. Up to 1.664 Gbps per lane. Leave NC if unused."+ },+ {+ "number": "16",+ "name": "CSI_D1P",+ "type": "output",+ "description": "MIPI CSI-2 differential data lane 1, positive. Up to 1.664 Gbps per lane. Leave NC if unused."+ },+ {+ "number": "17",+ "name": "VDD18_CSI",+ "type": "power_in",+ "description": "1.8 V (\u00b15%) supply for the CSI-2 output block. Requires 1 \u00b5F and 0.01 \u00b5F caps to GND."+ },+ {+ "number": "18",+ "name": "CSI_CLK1N",+ "type": "output",+ "description": "MIPI CSI-2 differential clock lane 1, negative. Used when the second CSI-2 clock/data pair is enabled (e.g. replicate mode with CSI_D2P/N, CSI_D3P/N)."+ },+ {+ "number": "19",+ "name": "CSI_CLK1P",+ "type": "output",+ "description": "MIPI CSI-2 differential clock lane 1, positive. Used when the second CSI-2 clock/data pair is enabled (e.g. replicate mode with CSI_D2P/N, CSI_D3P/N)."+ },+ {+ "number": "20",+ "name": "VDD11_CSI",+ "type": "power_in",+ "description": "1.1 V core supply / internal-regulator decoupling for CSI-2 block. If VDD_SEL=LOW, decouple only (0.01-0.1 \u00b5F + 4.7 \u00b5F to GND). If VDD_SEL=HIGH, drive from external 1.1 V (0.01 \u00b5F + 10 \u00b5F to GND)."+ },+ {+ "number": "21",+ "name": "CSI_D2N",+ "type": "output",+ "description": "MIPI CSI-2 differential data lane 2, negative. In replicate mode this lane is paired with CSI_CLK1P/N. Leave NC if unused."+ },+ {+ "number": "22",+ "name": "CSI_D2P",+ "type": "output",+ "description": "MIPI CSI-2 differential data lane 2, positive. In replicate mode this lane is paired with CSI_CLK1P/N. Leave NC if unused."+ },+ {+ "number": "23",+ "name": "CSI_D3N",+ "type": "output",+ "description": "MIPI CSI-2 differential data lane 3, negative. In replicate mode this lane is paired with CSI_CLK1P/N. Leave NC if unused."+ },+ {+ "number": "24",+ "name": "CSI_D3P",+ "type": "output",+ "description": "MIPI CSI-2 differential data lane 3, positive. In replicate mode this lane is paired with CSI_CLK1P/N. Leave NC if unused."+ },+ {+ "number": "25",+ "name": "GPIO3/INTB",+ "type": "bidirectional",+ "description": "Muxed GPIO3 / active-low interrupt. Open-drain; pull up 4.7 k\u03a9 to VDDIO. Function is chosen by register configuration."+ },+ {+ "number": "26",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General-purpose I/O. Configurable to mirror a serializer GPIO or follow local register settings. Powered from VDDIO. Internal 35 k\u03a9 pull-down; disabled at power-up."+ },+ {+ "number": "27",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-purpose I/O. Configurable to mirror a serializer GPIO or follow local register settings. Powered from VDDIO. Internal 35 k\u03a9 pull-down; disabled at power-up."+ },+ {+ "number": "28",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "General-purpose I/O. Configurable to mirror a serializer GPIO or follow local register settings. Powered from VDDIO. Internal 35 k\u03a9 pull-down; disabled at power-up."+ },+ {+ "number": "29",+ "name": "VDDIO",+ "type": "power_in",+ "description": "LVCMOS I/O supply: 1.8 V or 3.3 V. When at 1.8 V, must track V(VDD18) within \u00b1100 mV. Requires 1 \u00b5F + 0.01 \u00b5F cap to GND per VDDIO pin."+ },+ {+ "number": "30",+ "name": "PDB",+ "type": "input",+ "description": "Active-high power-down inverted input. PDB=1.8 V enables the device (normal operation); PDB=0 powers it down with CSI-2 Tx tri-stated. Internal 50 k\u03a9 pull-down; 3.3-V tolerant."+ },+ {+ "number": "31",+ "name": "VDD18_FPD1",+ "type": "power_in",+ "description": "1.8 V (\u00b15%) analog supply for FPD-Link III port 1. Requires 10 \u00b5F + 0.1 \u00b5F caps to GND."+ },+ {+ "number": "32",+ "name": "RIN1+",+ "type": "bidirectional",+ "description": "FPD-Link III receive channel 1, positive. Differential receiver and bidirectional back-channel driver; must be AC-coupled. Leave NC and disable via RX_PORT_CTL bit 1 if unused."+ },+ {+ "number": "33",+ "name": "RIN1-",+ "type": "bidirectional",+ "description": "FPD-Link III receive channel 1, negative. Differential receiver and bidirectional back-channel driver; must be AC-coupled. Leave NC and disable via RX_PORT_CTL bit 1 if unused."+ },+ {+ "number": "34",+ "name": "VDD11_FPD1",+ "type": "power_in",+ "description": "1.1 V core supply / internal-regulator decoupling for FPD-Link III port 1. If VDD_SEL=LOW, decouple only. If VDD_SEL=HIGH, drive from external 1.1 V (0.01 \u00b5F cap plus a 10 \u00b5F cap shared with VDD11_FPD0)."+ },+ {+ "number": "35",+ "name": "IDX",+ "type": "input",+ "description": "I2C primary-device address select strap. Sampled at enable to set default I2C address; typically driven by a resistor divider from VDD18 to GND. Internal pull-down."+ },+ {+ "number": "36",+ "name": "VDD18_P1",+ "type": "power_in",+ "description": "1.8 V (\u00b15%) supply for FPD-Link III port 1 digital. Requires 0.01 \u00b5F cap per pin plus 10 \u00b5F bulk decoupling."+ },+ {+ "number": "37",+ "name": "MODE",+ "type": "input",+ "description": "Mode-select strap. Sampled voltage sets operating mode (see Table 7-2). Typically driven by a resistor divider from VDD18 to GND. Internal pull-down."+ },+ {+ "number": "38",+ "name": "CMLOUTP",+ "type": "output",+ "description": "Monitor loop-through differential driver output, positive. Typically routed to test points; terminate with 100-\u03a9 differential load when monitoring."+ },+ {+ "number": "39",+ "name": "CMLOUTN",+ "type": "output",+ "description": "Monitor loop-through differential driver output, negative. Typically routed to test points; terminate with 100-\u03a9 differential load when monitoring."+ },+ {+ "number": "40",+ "name": "VDD18_FPD0",+ "type": "power_in",+ "description": "1.8 V (\u00b15%) analog supply for FPD-Link III port 0. Requires 10 \u00b5F + 0.1 \u00b5F caps to GND."+ },+ {+ "number": "41",+ "name": "RIN0+",+ "type": "bidirectional",+ "description": "FPD-Link III receive channel 0, positive. Differential receiver and bidirectional back-channel driver; must be AC-coupled. Leave NC and disable via RX_PORT_CTL bit 0 if unused."+ },+ {+ "number": "42",+ "name": "RIN0-",+ "type": "bidirectional",+ "description": "FPD-Link III receive channel 0, negative. Differential receiver and bidirectional back-channel driver; must be AC-coupled. Leave NC and disable via RX_PORT_CTL bit 0 if unused."+ },+ {+ "number": "43",+ "name": "VDD11_FPD0",+ "type": "power_in",+ "description": "1.1 V core supply / internal-regulator decoupling for FPD-Link III port 0. If VDD_SEL=LOW, decouple only. If VDD_SEL=HIGH, drive from external 1.1 V (0.01 \u00b5F cap plus a 10 \u00b5F cap shared with VDD11_FPD1)."+ },+ {+ "number": "44",+ "name": "RES",+ "type": "passive",+ "description": "Reserved. Must be tied to GND for normal operation. Internal pull-down."+ },+ {+ "number": "45",+ "name": "VDD18_P0",+ "type": "power_in",+ "description": "1.8 V (\u00b15%) supply for FPD-Link III port 0 digital. Requires 0.01 \u00b5F cap per pin plus 10 \u00b5F bulk decoupling."+ },+ {+ "number": "46",+ "name": "VDD_SEL",+ "type": "input",+ "description": "Internal-LDO / external-VDD11 select strap. LOW = internal 1.1 V LDO drives VDD11 pins (decouple only). HIGH = supply external 1.1 V \u00b15% to VDD11 pins after VDD18 is up. Internal pull-down."+ },+ {+ "number": "47",+ "name": "PASS",+ "type": "output",+ "description": "PASS status output. H = pass conditions met (in BIST mode: error-free forward-channel transmission). L = one or more errors. Leave NC if unused."+ },+ {+ "number": "48",+ "name": "LOCK",+ "type": "output",+ "description": "FPD-Link III lock-status output. H = receiver locked and Rx port(s) active; L = unlocked. Can be configured as a logical-AND of both Rx ports. Leave NC if unused."+ },+ {+ "number": "DAP",+ "name": "GND",+ "type": "power_in",+ "description": "Exposed die-attach pad on the bottom of the QFN. Must be soldered to the board ground plane (GND) for thermal and electrical performance."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ds90ub936-q1",+ "pages": null,+ "sha256": "ba583efca4a0898d",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Texas Instruments",+ "Package": "VQFN-48-EP(7x7)",+ "Category": "Interface",+ "Pins": "49"+ }+ },+ "variants": [+ {+ "mpn": "DS90UB936TRGZRQ1",+ "kind": "packaging"+ },+ {+ "mpn": "DS90UB936TRGZTQ1",+ "kind": "unknown"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "ds90ub936trgzrq1"+ ],+ "discovery_pitch": "DS90UB936TRGZRQ1 (Texas Instruments) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +394,5 @@ "docs/ds90ub936trgzrq1-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }