DS90UB936TRGZRQ1

@@ -0,0 +1,92 @@+# DS90UB936TRGZRQ1++**Texas Instruments** · LVDS ICs · VQFN-48-EP(7x7)++DS90UB936TRGZRQ1 from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | I2C_SDA | bidirectional | I2C serial data line for bidirectional control-bus communication. Open-drain, 3.3-V tolerant. External 2 kΩ-4.7 kΩ pull-up to 1.8 V or 3.3 V required. |+| 2 | I2C_SCL | bidirectional | I2C serial clock line for bidirectional control-bus communication. Open-drain, 3.3-V tolerant. External 2 kΩ-4.7 kΩ pull-up to 1.8 V or 3.3 V required. |+| 3 | VDD11_D | power_in | 1.1 V core-digital supply / internal-regulator decoupling. If VDD_SEL=LOW, do not tie to a 1.1-V rail (internal LDO drives); requires 0.01-0.1 µF and 4.7 µF caps to GND. If VDD_SEL=HIGH, connect to external 1.1 V ±5%. |+| 4 | XOUT | output | Crystal oscillator output. Drive a 23-26 MHz crystal across XIN/XOUT, or leave NC when an external reference clock drives XIN/REFCLK. |+| 5 | XIN/REFCLK | input | Reference-clock input or crystal-oscillator input. Accepts a 23-26 MHz reference (100 ppm) or one leg of a 23-26 MHz crystal to XOUT. |+| 6 | BISTEN | input | Built-in self-test enable. H = BIST enabled, L = disabled. Internal pull-down; tie directly to GND if unused. |+| 7 | VDDIO | power_in | LVCMOS I/O supply: 1.8 V or 3.3 V. When at 1.8 V, must track V(VDD18) within ±100 mV. Requires 1 µF + 0.01 µF cap to GND per VDDIO pin. |+| 8 | GPIO6 | bidirectional | General-purpose I/O. Configurable to mirror a serializer GPIO or follow local register settings. Powered from VDDIO. Internal 35 kΩ pull-down; disabled at power-up. |+| 9 | GPIO5 | bidirectional | General-purpose I/O. Configurable to mirror a serializer GPIO or follow local register settings. Powered from VDDIO. Internal 35 kΩ pull-down; disabled at power-up. |+| 10 | GPIO4 | bidirectional | General-purpose I/O. Configurable to mirror a serializer GPIO or follow local register settings. Powered from VDDIO. Internal 35 kΩ pull-down; disabled at power-up. |+| 11 | CSI_CLK0N | output | MIPI CSI-2 differential clock lane 0, negative. DPHY output from FPD-Link III deserializer to host SoC. |+| 12 | CSI_CLK0P | output | MIPI CSI-2 differential clock lane 0, positive. DPHY output from FPD-Link III deserializer to host SoC. |+| 13 | CSI_D0N | output | MIPI CSI-2 differential data lane 0, negative. Up to 1.664 Gbps per lane. Leave NC if unused. |+| 14 | CSI_D0P | output | MIPI CSI-2 differential data lane 0, positive. Up to 1.664 Gbps per lane. Leave NC if unused. |+| 15 | CSI_D1N | output | MIPI CSI-2 differential data lane 1, negative. Up to 1.664 Gbps per lane. Leave NC if unused. |+| 16 | CSI_D1P | output | MIPI CSI-2 differential data lane 1, positive. Up to 1.664 Gbps per lane. Leave NC if unused. |+| 17 | VDD18_CSI | power_in | 1.8 V (±5%) supply for the CSI-2 output block. Requires 1 µF and 0.01 µF caps to GND. |+| 18 | CSI_CLK1N | output | MIPI CSI-2 differential clock lane 1, negative. Used when the second CSI-2 clock/data pair is enabled (e.g. replicate mode with CSI_D2P/N, CSI_D3P/N). |+| 19 | CSI_CLK1P | output | MIPI CSI-2 differential clock lane 1, positive. Used when the second CSI-2 clock/data pair is enabled (e.g. replicate mode with CSI_D2P/N, CSI_D3P/N). |+| 20 | VDD11_CSI | power_in | 1.1 V core supply / internal-regulator decoupling for CSI-2 block. If VDD_SEL=LOW, decouple only (0.01-0.1 µF + 4.7 µF to GND). If VDD_SEL=HIGH, drive from external 1.1 V (0.01 µF + 10 µF to GND). |+| 21 | CSI_D2N | output | MIPI CSI-2 differential data lane 2, negative. In replicate mode this lane is paired with CSI_CLK1P/N. Leave NC if unused. |+| 22 | CSI_D2P | output | MIPI CSI-2 differential data lane 2, positive. In replicate mode this lane is paired with CSI_CLK1P/N. Leave NC if unused. |+| 23 | CSI_D3N | output | MIPI CSI-2 differential data lane 3, negative. In replicate mode this lane is paired with CSI_CLK1P/N. Leave NC if unused. |+| 24 | CSI_D3P | output | MIPI CSI-2 differential data lane 3, positive. In replicate mode this lane is paired with CSI_CLK1P/N. Leave NC if unused. |+| 25 | GPIO3/INTB | bidirectional | Muxed GPIO3 / active-low interrupt. Open-drain; pull up 4.7 kΩ to VDDIO. Function is chosen by register configuration. |+| 26 | GPIO2 | bidirectional | General-purpose I/O. Configurable to mirror a serializer GPIO or follow local register settings. Powered from VDDIO. Internal 35 kΩ pull-down; disabled at power-up. |+| 27 | GPIO1 | bidirectional | General-purpose I/O. Configurable to mirror a serializer GPIO or follow local register settings. Powered from VDDIO. Internal 35 kΩ pull-down; disabled at power-up. |+| 28 | GPIO0 | bidirectional | General-purpose I/O. Configurable to mirror a serializer GPIO or follow local register settings. Powered from VDDIO. Internal 35 kΩ pull-down; disabled at power-up. |+| 29 | VDDIO | power_in | LVCMOS I/O supply: 1.8 V or 3.3 V. When at 1.8 V, must track V(VDD18) within ±100 mV. Requires 1 µF + 0.01 µF cap to GND per VDDIO pin. |+| 30 | PDB | input | Active-high power-down inverted input. PDB=1.8 V enables the device (normal operation); PDB=0 powers it down with CSI-2 Tx tri-stated. Internal 50 kΩ pull-down; 3.3-V tolerant. |+| 31 | VDD18_FPD1 | power_in | 1.8 V (±5%) analog supply for FPD-Link III port 1. Requires 10 µF + 0.1 µF caps to GND. |+| 32 | RIN1+ | bidirectional | FPD-Link III receive channel 1, positive. Differential receiver and bidirectional back-channel driver; must be AC-coupled. Leave NC and disable via RX_PORT_CTL bit 1 if unused. |+| 33 | RIN1- | bidirectional | FPD-Link III receive channel 1, negative. Differential receiver and bidirectional back-channel driver; must be AC-coupled. Leave NC and disable via RX_PORT_CTL bit 1 if unused. |+| 34 | VDD11_FPD1 | power_in | 1.1 V core supply / internal-regulator decoupling for FPD-Link III port 1. If VDD_SEL=LOW, decouple only. If VDD_SEL=HIGH, drive from external 1.1 V (0.01 µF cap plus a 10 µF cap shared with VDD11_FPD0). |+| 35 | IDX | input | I2C primary-device address select strap. Sampled at enable to set default I2C address; typically driven by a resistor divider from VDD18 to GND. Internal pull-down. |+| 36 | VDD18_P1 | power_in | 1.8 V (±5%) supply for FPD-Link III port 1 digital. Requires 0.01 µF cap per pin plus 10 µF bulk decoupling. |+| 37 | MODE | input | Mode-select strap. Sampled voltage sets operating mode (see Table 7-2). Typically driven by a resistor divider from VDD18 to GND. Internal pull-down. |+| 38 | CMLOUTP | output | Monitor loop-through differential driver output, positive. Typically routed to test points; terminate with 100-Ω differential load when monitoring. |+| 39 | CMLOUTN | output | Monitor loop-through differential driver output, negative. Typically routed to test points; terminate with 100-Ω differential load when monitoring. |+| 40 | VDD18_FPD0 | power_in | 1.8 V (±5%) analog supply for FPD-Link III port 0. Requires 10 µF + 0.1 µF caps to GND. |+| 41 | RIN0+ | bidirectional | FPD-Link III receive channel 0, positive. Differential receiver and bidirectional back-channel driver; must be AC-coupled. Leave NC and disable via RX_PORT_CTL bit 0 if unused. |+| 42 | RIN0- | bidirectional | FPD-Link III receive channel 0, negative. Differential receiver and bidirectional back-channel driver; must be AC-coupled. Leave NC and disable via RX_PORT_CTL bit 0 if unused. |+| 43 | VDD11_FPD0 | power_in | 1.1 V core supply / internal-regulator decoupling for FPD-Link III port 0. If VDD_SEL=LOW, decouple only. If VDD_SEL=HIGH, drive from external 1.1 V (0.01 µF cap plus a 10 µF cap shared with VDD11_FPD1). |+| 44 | RES | passive | Reserved. Must be tied to GND for normal operation. Internal pull-down. |+| 45 | VDD18_P0 | power_in | 1.8 V (±5%) supply for FPD-Link III port 0 digital. Requires 0.01 µF cap per pin plus 10 µF bulk decoupling. |+| 46 | VDD_SEL | input | Internal-LDO / external-VDD11 select strap. LOW = internal 1.1 V LDO drives VDD11 pins (decouple only). HIGH = supply external 1.1 V ±5% to VDD11 pins after VDD18 is up. Internal pull-down. |+| 47 | PASS | output | PASS status output. H = pass conditions met (in BIST mode: error-free forward-channel transmission). L = one or more errors. Leave NC if unused. |+| 48 | LOCK | output | FPD-Link III lock-status output. H = receiver locked and Rx port(s) active; L = unlocked. Can be configured as a logical-AND of both Rx ports. Leave NC if unused. |+| DAP | GND | power_in | Exposed die-attach pad on the bottom of the QFN. Must be soldered to the board ground plane (GND) for thermal and electrical performance. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | Interface |+| Pins | 49 |++## Ordering variants++Same part, different packaging or reel option.++- `DS90UB936TRGZRQ1`+- `DS90UB936TRGZTQ1`++## CAD (KiCad official)++- Symbol: `DS90UB936TRGZRQ1`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds90ub936-q1) (None pp, sha256 `ba583efca4a0898d`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ds90ub936trgzrq1-datasheet.pdf)