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DS90UB935TRHBRQ1
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Texas Instruments Serializers / Deserializers, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+70@@ -0,0 +1,70 @@+# DS90UB935TRHBRQ1++**Texas Instruments** · Serializers / Deserializers · VQFN-32-EP(5x5)++DS90UB935TRHBRQ1 from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CSI_D1P | input | CSI-2 data lane 1 positive D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused. |+| 2 | CSI_D1N | input | CSI-2 data lane 1 negative D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused. |+| 3 | CSI_D0P | input | CSI-2 data lane 0 positive D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused. |+| 4 | CSI_D0N | input | CSI-2 data lane 0 negative D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused. |+| 5 | CSI_CLKP | input | CSI-2 clock positive D-PHY input; connect to a CSI-2 clock source with matched 100Ω (±5%) interconnect. |+| 6 | CSI_CLKN | input | CSI-2 clock negative D-PHY input; connect to a CSI-2 clock source with matched 100Ω (±5%) interconnect. |+| 7 | RES0 | input | Reserved pin; connect to GND. |+| 8 | PDB | input | Active-low power-down input with internal 1MΩ pull-down; high (1.8V) enables the device and resets registers to defaults, low powers it down; not 3.3V tolerant. |+| 9 | LPF1 | passive | PLL loop filter 1; connect as described in section 7.2.2.4 (0.022µF capacitor to VDDPLL). |+| 10 | VDDPLL_CAP | passive | Internal regulator decoupling connection, typically 10µF, 0.1µF and 0.01µF to ground; do not connect to an external supply rail. |+| 11 | VDDPLL | power_in | 1.8V (±5%) analog supply pin, typically decoupled with 1µF and 0.01µF to ground. |+| 12 | LPF2 | passive | PLL loop filter 2; connect as described in section 7.2.2.4 (0.1µF capacitor to GND). |+| 13 | DOUT- | bidirectional | FPD-Link III inverting input/output pin; must be AC-coupled. |+| 14 | DOUT+ | bidirectional | FPD-Link III non-inverting input/output pin; must be AC-coupled. |+| 15 | VDDDRV_CAP | passive | Internal regulator decoupling connection, typically 10µF, 0.1µF and 0.01µF to ground; do not connect to an external supply rail. |+| 16 | VDDDRV | power_in | 1.8V (±5%) analog supply pin, typically decoupled with 1µF and 0.01µF to ground. |+| 17 | GPIO_0 | bidirectional | General-purpose I/O with voltage-sense capability; defaults to input with 300kΩ (typ) internal pull-down at power-up. |+| 18 | GPIO_1 | bidirectional | General-purpose I/O with voltage-sense capability; defaults to input with 300kΩ (typ) internal pull-down at power-up. |+| 19 | CLK_OUT/IDX | bidirectional | Strap input at power-up sets I2C pull-up voltage and device address via resistor divider, then becomes CLK_OUT; minimum 35kΩ load when CLK_OUT is used, may be tied to GND if unused. |+| 20 | CLKIN | input | Reference clock input for non-synchronous external clock mode; may be left open if unused. |+| 21 | MODE | input | Mode select strap input sampled when PDB goes low to high, set by a resistor divider from VDD18 to GND. |+| 22 | RES1 | input | Reserved pin; do not connect (leave floating). |+| 23 | I2C_SDA | bidirectional | Open-drain I2C data pin; pull up to 1.8V or 3.3V according to IDX setting. |+| 24 | I2C_SCL | bidirectional | Open-drain I2C clock pin; pull up to 1.8V or 3.3V according to IDX setting. |+| 25 | VDDD | power_in | 1.8V (±5%) supply pin, typically decoupled with 1µF and 0.01µF to ground. |+| 26 | VDDD_CAP | passive | Internal regulator decoupling connection, typically 10µF, 0.1µF and 0.01µF to ground; do not connect to an external supply rail. |+| 27 | GPIO_2 | bidirectional | General-purpose I/O; defaults to input with 300kΩ (typ) internal pull-down at power-up. |+| 28 | GPIO_3 | bidirectional | General-purpose I/O; defaults to input with 300kΩ (typ) internal pull-down at power-up. |+| 29 | CSI_D3P | input | CSI-2 data lane 3 positive D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused. |+| 30 | CSI_D3N | input | CSI-2 data lane 3 negative D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused. |+| 31 | CSI_D2P | input | CSI-2 data lane 2 positive D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused. |+| 32 | CSI_D2N | input | CSI-2 data lane 2 negative D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused. |+| 33 | GND | power_in | Exposed DAP, large metal contact at the center of the VQFN package; connect to the ground plane. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-32-EP(5x5) |+| Category | Communication Interface Chip/UART/485/232 |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `DS90UB935TRHBRQ1`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `ds90ub935trhbrq1-etched.step` / `ds90ub935trhbrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ds90ub935trhbrq1.step` / `ds90ub935trhbrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ds90ub935-q1) (88 pp, sha256 `e402e3a7c9adfc08`, retrieved 2026-10-06, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ds90ub935trhbrq1-datasheet.pdf)
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connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused."+ },+ {+ "number": "2",+ "name": "CSI_D1N",+ "type": "input",+ "description": "CSI-2 data lane 1 negative D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused."+ },+ {+ "number": "3",+ "name": "CSI_D0P",+ "type": "input",+ "description": "CSI-2 data lane 0 positive D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused."+ },+ {+ "number": "4",+ "name": "CSI_D0N",+ "type": "input",+ "description": "CSI-2 data lane 0 negative D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused."+ },+ {+ "number": "5",+ "name": "CSI_CLKP",+ "type": "input",+ "description": "CSI-2 clock positive D-PHY input; connect to a CSI-2 clock source with matched 100Ω (±5%) interconnect."+ },+ {+ "number": "6",+ "name": "CSI_CLKN",+ "type": "input",+ "description": "CSI-2 clock negative D-PHY input; connect to a CSI-2 clock source with matched 100Ω (±5%) interconnect."+ },+ {+ "number": "7",+ "name": "RES0",+ "type": "input",+ "description": "Reserved pin; connect to GND."+ },+ {+ "number": "8",+ "name": "PDB",+ "type": "input",+ "description": "Active-low power-down input with internal 1MΩ pull-down; high (1.8V) enables the device and resets registers to defaults, low powers it down; not 3.3V tolerant."+ },+ {+ "number": "9",+ "name": "LPF1",+ "type": "passive",+ "description": "PLL loop filter 1; connect as described in section 7.2.2.4 (0.022µF capacitor to VDDPLL)."+ },+ {+ "number": "10",+ "name": "VDDPLL_CAP",+ "type": "passive",+ "description": "Internal regulator decoupling connection, typically 10µF, 0.1µF and 0.01µF to ground; do not connect to an external supply rail."+ },+ {+ "number": "11",+ "name": "VDDPLL",+ "type": "power_in",+ "description": "1.8V (±5%) analog supply pin, typically decoupled with 1µF and 0.01µF to ground."+ },+ {+ "number": "12",+ "name": "LPF2",+ "type": "passive",+ "description": "PLL loop filter 2; connect as described in section 7.2.2.4 (0.1µF capacitor to GND)."+ },+ {+ "number": "13",+ "name": "DOUT-",+ "type": "bidirectional",+ "description": "FPD-Link III inverting input/output pin; must be AC-coupled."+ },+ {+ "number": "14",+ "name": "DOUT+",+ "type": "bidirectional",+ "description": "FPD-Link III non-inverting input/output pin; must be AC-coupled."+ },+ {+ "number": "15",+ "name": "VDDDRV_CAP",+ "type": "passive",+ "description": "Internal regulator decoupling connection, typically 10µF, 0.1µF and 0.01µF to ground; do not connect to an external supply rail."+ },+ {+ "number": "16",+ "name": "VDDDRV",+ "type": "power_in",+ "description": "1.8V (±5%) analog supply pin, typically decoupled with 1µF and 0.01µF to ground."+ },+ {+ "number": "17",+ "name": "GPIO_0",+ "type": "bidirectional",+ "description": "General-purpose I/O with voltage-sense capability; defaults to input with 300kΩ (typ) internal pull-down at power-up."+ },+ {+ "number": "18",+ "name": "GPIO_1",+ "type": "bidirectional",+ "description": "General-purpose I/O with voltage-sense capability; defaults to input with 300kΩ (typ) internal pull-down at power-up."+ },+ {+ "number": "19",+ "name": "CLK_OUT/IDX",+ "type": "bidirectional",+ "description": "Strap input at power-up sets I2C pull-up voltage and device address via resistor divider, then becomes CLK_OUT; minimum 35kΩ load when CLK_OUT is used, may be tied to GND if unused."+ },+ {+ "number": "20",+ "name": "CLKIN",+ "type": "input",+ "description": "Reference clock input for non-synchronous external clock mode; may be left open if unused."+ },+ {+ "number": "21",+ "name": "MODE",+ "type": "input",+ "description": "Mode select strap input sampled when PDB goes low to high, set by a resistor divider from VDD18 to GND."+ },+ {+ "number": "22",+ "name": "RES1",+ "type": "input",+ "description": "Reserved pin; do not connect (leave floating)."+ },+ {+ "number": "23",+ "name": "I2C_SDA",+ "type": "bidirectional",+ "description": "Open-drain I2C data pin; pull up to 1.8V or 3.3V according to IDX setting."+ },+ {+ "number": "24",+ "name": "I2C_SCL",+ "type": "bidirectional",+ "description": "Open-drain I2C clock pin; pull up to 1.8V or 3.3V according to IDX setting."+ },+ {+ "number": "25",+ "name": "VDDD",+ "type": "power_in",+ "description": "1.8V (±5%) supply pin, typically decoupled with 1µF and 0.01µF to ground."+ },+ {+ "number": "26",+ "name": "VDDD_CAP",+ "type": "passive",+ "description": "Internal regulator decoupling connection, typically 10µF, 0.1µF and 0.01µF to ground; do not connect to an external supply rail."+ },+ {+ "number": "27",+ "name": "GPIO_2",+ "type": "bidirectional",+ "description": "General-purpose I/O; defaults to input with 300kΩ (typ) internal pull-down at power-up."+ },+ {+ "number": "28",+ "name": "GPIO_3",+ "type": "bidirectional",+ "description": "General-purpose I/O; defaults to input with 300kΩ (typ) internal pull-down at power-up."+ },+ {+ "number": "29",+ "name": "CSI_D3P",+ "type": "input",+ "description": "CSI-2 data lane 3 positive D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused."+ },+ {+ "number": "30",+ "name": "CSI_D3N",+ "type": "input",+ "description": "CSI-2 data lane 3 negative D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused."+ },+ {+ "number": "31",+ "name": "CSI_D2P",+ "type": "input",+ "description": "CSI-2 data lane 2 positive D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused."+ },+ {+ "number": "32",+ "name": "CSI_D2N",+ "type": "input",+ "description": "CSI-2 data lane 2 negative D-PHY input; connect to a CSI-2 source with matched 100Ω (±5%) interconnect, may be left floating if unused."+ },+ {+ "number": "33",+ "name": "GND",+ "type": "power_in",+ "description": "Exposed DAP, large metal contact at the center of the VQFN package; connect to the ground plane."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: PDB pin voltage rating: datasheet specifies pin cannot withstand 3.3V; absolute maximum is VDD + 0.3",+ "exposed pad 33 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 49,+ "cost_usd": 0.3876,+ "at": "2026-10-06T16:31:49"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ds90ub935-q1",+ "pages": 88,+ "sha256": "e402e3a7c9adfc08",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}