DS1302IDRG

@@ -0,0 +1,55 @@+# DS1302IDRG++**HANSCHIP semiconductor** · Real-time Clocks (RTC) · SOP-8++DS1302IDRG from HANSCHIP semiconductor, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VCC2 | power_in | Primary power supply input (main supply). Operating range 2.0 V to 5.5 V. Feeds the trickle-charge circuit that can charge a backup cell/cap on VCC1. |+| 2 | X1 | passive | Connection for a 32.768 kHz crystal oscillator (one terminal). Recommended crystal load capacitance CX = 6 pF typical. |+| 3 | X2 | passive | Connection for a 32.768 kHz crystal oscillator (other terminal). Pair with X1 across the crystal; CX ≈ 6 pF. |+| 4 | GND | power_in | Device ground reference (0 V). |+| 5 | RST | input | Reset / chip enable input, active high. Drive high to initiate a data transfer; drive low to terminate a transfer and place I/O into a high-impedance state. Must be low at power-up until VCC ≥ 2.5 V; when driving RST high, SCLK must be at logic 0. |+| 6 | I/O | bidirectional | Serial data input/output for the 3-wire interface. Command/data bits are clocked in on rising SCLK edges and read data is clocked out on falling SCLK edges. Goes high-impedance when RST is low. TTL-compatible at VCC = 5 V. |+| 7 | SCLK | input | Serial clock input for the 3-wire interface. Synchronizes shifting of command and data bytes on the I/O pin. Maximum clock rate 0.5 MHz at VCC = 2.5 V, 2.0 MHz at VCC = 5 V. |+| 8 | VCC1 | power_in | Backup power supply input (typically a Ni-Cd cell or supercap). Powers the RTC and RAM when VCC2 is absent; can be trickle-charged from VCC2 through selectable diode/resistor combinations (R1=2 kΩ, R2=4 kΩ, R3=8 kΩ; VTD ≈ 0.7 V). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | HANSCHIP semiconductor |+| Package | SOP-8 |+| Category | RTC |+| Pins | 8 |++## Ordering variants++- `DS1302IDRGDS1302CDRG`+- `DS1302IDRG`+- `DS1302IDRGDS1302CDRG4`+- `DS1302IDRG4`+- `DS1302IDRGDS1302CPG`+- `DS1302IDRGDS1302IPG`+- `DS1302IDRGDS1302CDGKRG`+- `DS1302IDRGDS1302IDGKRG`++## CAD (KiCad official)++- Symbol: `DS1302IDRG`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOP-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [HANSCHIP semiconductor datasheet](docs/ds1302idrg-datasheet.pdf) (15 pp, sha256 `6dfca75d1e1627dd`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ds1302idrg-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "ds1302idrg",+  "version": "0.1.0",+  "type": "component",+  "description": "HANSCHIP semiconductor Real-time Clocks (RTC), SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "rtc",+    "ds1302idrg"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "ds1302idrg.kicad_sym",+    "ds1302idrg.kicad_mod",+    "ds1302idrg.glb",+    "ds1302idrg.step",+    "ds1302idrg.lbr",+    "docs/hero.png",+    "docs/ds1302idrg-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file