DRV8703QRHBRQ1

@@ -0,0 +1,76 @@+# DRV8703QRHBRQ1++**Texas Instruments** · Motor Driver ICs · QFN-32-EP(5x5)++DRV8703QRHBRQ1 from Texas Instruments, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Device ground. Connect this pin to system ground. |+| 2 | IN1/PH | input | Input control pin. Logic depends on the MODE pin setting (IN1 in PWM/independent modes, PH in PH/EN mode). Has an internal pull-down resistor. |+| 3 | IN2/EN | input | Input control pin. Logic depends on the MODE pin setting (IN2 in PWM/independent modes, EN in PH/EN mode). Has an internal pull-down resistor. |+| 4 | SDO | output | SPI data output (open-drain). Requires an external pull-up resistor. |+| 5 | nSCS | input | SPI chip-select input, active low. Selects and enables the SPI interface. |+| 6 | SDI | input | SPI data input. Has an internal pull-down resistor. |+| 7 | SCLK | input | SPI clock input. Has an internal pull-down resistor. |+| 8 | nSLEEP | input | Sleep mode input, active low. Pulling low puts the device into low-power sleep with FET outputs Hi-Z. Has an internal pull-down resistor. |+| 9 | nWDFLT | output | Watchdog fault indicator (open-drain). Pulled low when a watchdog fault occurs; requires an external pull-up resistor. |+| 10 | nFAULT | output | Fault indicator (open-drain). Pulled low on any fault condition; requires an external pull-up resistor. |+| 11 | MODE | input | Mode control pin. Low selects H-bridge operation; high selects independent half-bridge operation. Connected to an internal resistor divider with internal pull-up and pull-down; latched at power-up or on wake from sleep. |+| 12 | DVDD | power_out | Internal 3.3 V logic regulator output. Bypass to GND with a 6.3 V, 1 µF ceramic capacitor. |+| 13 | GND | power_in | Device ground. Connect this pin to system ground. |+| 14 | AVDD | power_out | Internal 5 V analog regulator output. Bypass to GND with a 6.3 V, 1 µF ceramic capacitor. |+| 15 | VREF | input | Current-set reference input. Voltage on this pin sets the chopping current threshold (0.3 V to 3.6 V recommended). |+| 16 | SO | output | Shunt amplifier output. VSO = VSP × AV + offset. Do not place more than 1 nF of capacitance on this pin; max 5 mA load. |+| 17 | GND | power_in | Device ground. Connect this pin to system ground. |+| 18 | GH1 | output | High-side gate drive output for H-bridge 1. Connect to the gate of the high-side external N-channel MOSFET. |+| 19 | SH1 | input | High-side source sense for H-bridge 1. Connect to the source of the high-side external N-channel MOSFET (phase node). |+| 20 | GL1 | output | Low-side gate drive output for H-bridge 1. Connect to the gate of the low-side external N-channel MOSFET. |+| 21 | SP | input | Shunt amplifier positive input. Connect to the current-sense resistor. |+| 22 | SN | input | Shunt amplifier negative input. Connect to the current-sense resistor. |+| 23 | SL2 | input | Low-side source sense for H-bridge 2. Connect to the source of the low-side external N-channel MOSFET. |+| 24 | GL2 | output | Low-side gate drive output for H-bridge 2. Connect to the gate of the low-side external N-channel MOSFET. |+| 25 | SH2 | input | High-side source sense for H-bridge 2. Connect to the source of the high-side external N-channel MOSFET (phase node). |+| 26 | GH2 | output | High-side gate drive output for H-bridge 2. Connect to the gate of the high-side external N-channel MOSFET. |+| 27 | VDRAIN | input | High-side FET drain sense. Shared by both H-bridges; connects to the drains of the high-side external MOSFETs. |+| 28 | VM | power_in | Motor power supply input, 5.5 V to 45 V. Bypass to GND with a 0.1 µF ceramic capacitor and a minimum 10 µF bulk capacitor. |+| 29 | VCP | power_out | Charge pump output. Connect a 16 V, 1 µF ceramic capacitor between this pin and VM. |+| 30 | CPH | passive | Charge pump switching node (positive). Connect a 0.1 µF X7R capacitor rated for VM between CPH and CPL. |+| 31 | CPL | passive | Charge pump switching node (negative). Connect a 0.1 µF X7R capacitor rated for VM between CPH and CPL. |+| 32 | NC | unconnected | No connect. No internal connection; leave floating or tie to GND. |+| 33 | PAD | power_in | Exposed thermal pad on the underside of the package. Must be connected to system ground for electrical return and thermal dissipation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | QFN-32-EP(5x5) |+| Category | Power Supply Chip |+| Pins | 33 |++## Ordering variants++Same part, different packaging or reel option.++- `DRV8703QRHBRQ1`+- `DRV8703-Q1 RHB`++## CAD (KiCad official)++- Symbol: `DRV8703QRHBRQ1`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/ds/symlink/drv8702-q1.pdf) (63 pp, sha256 `ab99f0978331e55f`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8703qrhbrq1-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "drv8703qrhbrq1",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Motor Driver ICs, QFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "power supply chip",+    "drv8703qrhbrq1"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "drv8703qrhbrq1.kicad_sym",+    "drv8703qrhbrq1.kicad_mod",+    "drv8703qrhbrq1.glb",+    "drv8703qrhbrq1.step",+    "drv8703qrhbrq1.lbr",+    "docs/hero.png",+    "docs/drv8703qrhbrq1-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file