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drv8703qrhbrq1: factory component page (tier=lcsc)

Ray ·1435941a01 · ·parent 1466704
1 file changed +276−8
page.json+276−8
@@ -1,13 +1,286 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "drv8703qrhbrq1",+  "title": "DRV8703QRHBRQ1",+  "brief": "Texas Instruments Motor Driver ICs, QFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "Texas Instruments Motor Driver ICs, QFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "power supply chip",     "drv8703qrhbrq1"   ],+  "component": {+    "mpn": "DRV8703QRHBRQ1",+    "manufacturer": "Texas Instruments",+    "package": "QFN-32-EP(5x5)",+    "pin_count": 33,+    "category": "Power Supply Chip",+    "subcategory": "Motor Driver ICs",+    "datasheet": "https://www.ti.com/cn/lit/ds/symlink/drv8702-q1.pdf",+    "parts": {+      "symbol": "drv8703qrhbrq1.kicad_sym",+      "footprint": "drv8703qrhbrq1.kicad_mod",+      "model_3d": "drv8703qrhbrq1.glb",+      "model_3d_step": "drv8703qrhbrq1.step",+      "lbr": "drv8703qrhbrq1.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "GND",+        "type": "power_in",+        "description": "Device ground. Connect this pin to system ground."+      },+      {+        "number": "2",+        "name": "IN1/PH",+        "type": "input",+        "description": "Input control pin. Logic depends on the MODE pin setting (IN1 in PWM/independent modes, PH in PH/EN mode). Has an internal pull-down resistor."+      },+      {+        "number": "3",+        "name": "IN2/EN",+        "type": "input",+        "description": "Input control pin. Logic depends on the MODE pin setting (IN2 in PWM/independent modes, EN in PH/EN mode). Has an internal pull-down resistor."+      },+      {+        "number": "4",+        "name": "SDO",+        "type": "output",+        "description": "SPI data output (open-drain). Requires an external pull-up resistor."+      },+      {+        "number": "5",+        "name": "nSCS",+        "type": "input",+        "description": "SPI chip-select input, active low. Selects and enables the SPI interface."+      },+      {+        "number": "6",+        "name": "SDI",+        "type": "input",+        "description": "SPI data input. Has an internal pull-down resistor."+      },+      {+        "number": "7",+        "name": "SCLK",+        "type": "input",+        "description": "SPI clock input. Has an internal pull-down resistor."+      },+      {+        "number": "8",+        "name": "nSLEEP",+        "type": "input",+        "description": "Sleep mode input, active low. Pulling low puts the device into low-power sleep with FET outputs Hi-Z. Has an internal pull-down resistor."+      },+      {+        "number": "9",+        "name": "nWDFLT",+        "type": "output",+        "description": "Watchdog fault indicator (open-drain). Pulled low when a watchdog fault occurs; requires an external pull-up resistor."+      },+      {+        "number": "10",+        "name": "nFAULT",+        "type": "output",+        "description": "Fault indicator (open-drain). Pulled low on any fault condition; requires an external pull-up resistor."+      },+      {+        "number": "11",+        "name": "MODE",+        "type": "input",+        "description": "Mode control pin. Low selects H-bridge operation; high selects independent half-bridge operation. Connected to an internal resistor divider with internal pull-up and pull-down; latched at power-up or on wake from sleep."+      },+      {+        "number": "12",+        "name": "DVDD",+        "type": "power_out",+        "description": "Internal 3.3 V logic regulator output. Bypass to GND with a 6.3 V, 1 \u00b5F ceramic capacitor."+      },+      {+        "number": "13",+        "name": "GND",+        "type": "power_in",+        "description": "Device ground. Connect this pin to system ground."+      },+      {+        "number": "14",+        "name": "AVDD",+        "type": "power_out",+        "description": "Internal 5 V analog regulator output. Bypass to GND with a 6.3 V, 1 \u00b5F ceramic capacitor."+      },+      {+        "number": "15",+        "name": "VREF",+        "type": "input",+        "description": "Current-set reference input. Voltage on this pin sets the chopping current threshold (0.3 V to 3.6 V recommended)."+      },+      {+        "number": "16",+        "name": "SO",+        "type": "output",+        "description": "Shunt amplifier output. VSO = VSP \u00d7 AV + offset. Do not place more than 1 nF of capacitance on this pin; max 5 mA load."+      },+      {+        "number": "17",+        "name": "GND",+        "type": "power_in",+        "description": "Device ground. Connect this pin to system ground."+      },+      {+        "number": "18",+        "name": "GH1",+        "type": "output",+        "description": "High-side gate drive output for H-bridge 1. Connect to the gate of the high-side external N-channel MOSFET."+      },+      {+        "number": "19",+        "name": "SH1",+        "type": "input",+        "description": "High-side source sense for H-bridge 1. Connect to the source of the high-side external N-channel MOSFET (phase node)."+      },+      {+        "number": "20",+        "name": "GL1",+        "type": "output",+        "description": "Low-side gate drive output for H-bridge 1. Connect to the gate of the low-side external N-channel MOSFET."+      },+      {+        "number": "21",+        "name": "SP",+        "type": "input",+        "description": "Shunt amplifier positive input. Connect to the current-sense resistor."+      },+      {+        "number": "22",+        "name": "SN",+        "type": "input",+        "description": "Shunt amplifier negative input. Connect to the current-sense resistor."+      },+      {+        "number": "23",+        "name": "SL2",+        "type": "input",+        "description": "Low-side source sense for H-bridge 2. Connect to the source of the low-side external N-channel MOSFET."+      },+      {+        "number": "24",+        "name": "GL2",+        "type": "output",+        "description": "Low-side gate drive output for H-bridge 2. Connect to the gate of the low-side external N-channel MOSFET."+      },+      {+        "number": "25",+        "name": "SH2",+        "type": "input",+        "description": "High-side source sense for H-bridge 2. Connect to the source of the high-side external N-channel MOSFET (phase node)."+      },+      {+        "number": "26",+        "name": "GH2",+        "type": "output",+        "description": "High-side gate drive output for H-bridge 2. Connect to the gate of the high-side external N-channel MOSFET."+      },+      {+        "number": "27",+        "name": "VDRAIN",+        "type": "input",+        "description": "High-side FET drain sense. Shared by both H-bridges; connects to the drains of the high-side external MOSFETs."+      },+      {+        "number": "28",+        "name": "VM",+        "type": "power_in",+        "description": "Motor power supply input, 5.5 V to 45 V. Bypass to GND with a 0.1 \u00b5F ceramic capacitor and a minimum 10 \u00b5F bulk capacitor."+      },+      {+        "number": "29",+        "name": "VCP",+        "type": "power_out",+        "description": "Charge pump output. Connect a 16 V, 1 \u00b5F ceramic capacitor between this pin and VM."+      },+      {+        "number": "30",+        "name": "CPH",+        "type": "passive",+        "description": "Charge pump switching node (positive). Connect a 0.1 \u00b5F X7R capacitor rated for VM between CPH and CPL."+      },+      {+        "number": "31",+        "name": "CPL",+        "type": "passive",+        "description": "Charge pump switching node (negative). Connect a 0.1 \u00b5F X7R capacitor rated for VM between CPH and CPL."+      },+      {+        "number": "32",+        "name": "NC",+        "type": "unconnected",+        "description": "No connect. No internal connection; leave floating or tie to GND."+      },+      {+        "number": "33",+        "name": "PAD",+        "type": "power_in",+        "description": "Exposed thermal pad on the underside of the package. Must be connected to system ground for electrical return and thermal dissipation."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/ds/symlink/drv8702-q1.pdf",+        "pages": 63,+        "sha256": "ab99f0978331e55f",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 33,+        "described": 33,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "Texas Instruments",+      "Package": "QFN-32-EP(5x5)",+      "Category": "Power Supply Chip",+      "Pins": "33"+    }+  },+  "variants": [+    {+      "mpn": "DRV8703QRHBRQ1",+      "kind": "packaging"+    },+    {+      "mpn": "DRV8703-Q1 RHB",+      "kind": "unknown"+    }+  ],+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "drv8703qrhbrq1"+  ],+  "discovery_pitch": "DRV8703QRHBRQ1 (Texas Instruments) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +298,5 @@     "docs/drv8703qrhbrq1-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file