component
DRV8353RSRGZR
Public Made by Adomby adom
Texas Instruments Brushless DC (BLDC) Motor Driver, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
drv8353rsrgzr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
2 files changed
+92−12
package.json+50−10@@ -59,7 +59,7 @@ "number": "2", "name": "VGLS", "type": "power_out",- "description": "11-V internal regulator output. Connect a X5R or X7R, 1-\u00b5F, 16-V ceramic capacitor between the VGLS and GND pins."+ "description": "11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins." }, { "number": "3",@@ -77,7 +77,7 @@ "number": "5", "name": "VM", "type": "power_in",- "description": "Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage with 0.1-\u00b5F and \u226510-\u00b5F local capacitance."+ "description": "Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage with 0.1-µF and ≥10-µF local capacitance." }, { "number": "6",@@ -89,7 +89,7 @@ "number": "7", "name": "VCP", "type": "power_out",- "description": "Charge pump output. Connect a X5R or X7R, 1-\u00b5F, 16-V ceramic capacitor between the VCP and VDRAIN pins."+ "description": "Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins." }, { "number": "8",@@ -203,7 +203,7 @@ "number": "26", "name": "VREF", "type": "power_out",- "description": "Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-\u00b5F, 6.3-V ceramic capacitor between the VREF and AGND pins."+ "description": "Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins." }, { "number": "27",@@ -245,7 +245,7 @@ "number": "33", "name": "ENABLE", "type": "input",- "description": "Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-\u00b5s low pulse can be used to reset fault conditions."+ "description": "Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions." }, { "number": "34",@@ -287,7 +287,7 @@ "number": "40", "name": "DVDD", "type": "power_out",- "description": "5-V internal regulator output. Connect a X5R or X7R, 1-\u00b5F, 6.3-V ceramic capacitor between the DVDD and DGND pins. This regulator can source up to 10 mA externally."+ "description": "5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins. This regulator can source up to 10 mA externally." }, { "number": "41",@@ -311,13 +311,13 @@ "number": "44", "name": "VCC", "type": "power_out",- "description": "7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-\u00b5F, 16-V ceramic capacitor between the VCC and GND pins."+ "description": "7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-µF, 16-V ceramic capacitor between the VCC and GND pins." }, { "number": "45", "name": "BST", "type": "power_out",- "description": "Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-\u00b5F, 16-V capacitor between the BST and SW pins."+ "description": "Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-µF, 16-V capacitor between the BST and SW pins." }, { "number": "46",@@ -378,6 +378,46 @@ "viewers": { "symbol": "viewers/symbol.html", "footprint": "viewers/footprint.html"- }+ },+ "models_3d": [+ {+ "file": "drv8353rsrgzr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7.0,+ 7.0,+ 0.77+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "drv8353rsrgzr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7.0,+ 7.0,+ 0.77+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "3427b6c84ffcecfca23b3c4a602e2375f1d3578ae3bd6ba1bbf4d6c3f3a22ae5",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ] }-}+}
page.json+42−2@@ -363,7 +363,47 @@ "viewers": { "symbol": "viewers/symbol.html", "footprint": "viewers/footprint.html"- }+ },+ "models_3d": [+ {+ "file": "drv8353rsrgzr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7.0,+ 7.0,+ 0.77+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "drv8353rsrgzr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7.0,+ 7.0,+ 0.77+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "3427b6c84ffcecfca23b3c4a602e2375f1d3578ae3bd6ba1bbf4d6c3f3a22ae5",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ] }, "metadata": { "specs": {@@ -411,4 +451,4 @@ "public": true }, "updated_at": "2026-09-24T20:00:13.508Z"-}+}