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Set visibility: public

Ray ·982f0d804c · ·parent dcb4ee5
1 file changed +12−9
page.json+12−9
@@ -44,7 +44,7 @@         "number": "2",         "name": "VGLS",         "type": "power_out",-        "description": "11-V internal regulator output. Connect a X5R or X7R, 1-\u00b5F, 16-V ceramic capacitor between the VGLS and GND pins."+        "description": "11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins."       },       {         "number": "3",@@ -62,7 +62,7 @@         "number": "5",         "name": "VM",         "type": "power_in",-        "description": "Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage with 0.1-\u00b5F and \u226510-\u00b5F local capacitance."+        "description": "Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage with 0.1-µF and ≥10-µF local capacitance."       },       {         "number": "6",@@ -74,7 +74,7 @@         "number": "7",         "name": "VCP",         "type": "power_out",-        "description": "Charge pump output. Connect a X5R or X7R, 1-\u00b5F, 16-V ceramic capacitor between the VCP and VDRAIN pins."+        "description": "Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins."       },       {         "number": "8",@@ -188,7 +188,7 @@         "number": "26",         "name": "VREF",         "type": "power_out",-        "description": "Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-\u00b5F, 6.3-V ceramic capacitor between the VREF and AGND pins."+        "description": "Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins."       },       {         "number": "27",@@ -230,7 +230,7 @@         "number": "33",         "name": "ENABLE",         "type": "input",-        "description": "Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-\u00b5s low pulse can be used to reset fault conditions."+        "description": "Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions."       },       {         "number": "34",@@ -272,7 +272,7 @@         "number": "40",         "name": "DVDD",         "type": "power_out",-        "description": "5-V internal regulator output. Connect a X5R or X7R, 1-\u00b5F, 6.3-V ceramic capacitor between the DVDD and DGND pins. This regulator can source up to 10 mA externally."+        "description": "5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins. This regulator can source up to 10 mA externally."       },       {         "number": "41",@@ -296,13 +296,13 @@         "number": "44",         "name": "VCC",         "type": "power_out",-        "description": "7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-\u00b5F, 16-V ceramic capacitor between the VCC and GND pins."+        "description": "7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-µF, 16-V ceramic capacitor between the VCC and GND pins."       },       {         "number": "45",         "name": "BST",         "type": "power_out",-        "description": "Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-\u00b5F, 16-V capacitor between the BST and SW pins."+        "description": "Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-µF, 16-V capacitor between the BST and SW pins."       },       {         "number": "46",@@ -406,5 +406,8 @@     "docs/drv8353rsrgzr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file