DRV8350SRTVR

@@ -0,0 +1,86 @@+# DRV8350SRTVR++**Texas Instruments** · Brushless DC (BLDC) Motor Driver · WQFN-32-EP(5x5)++DRV8350SRTVR from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CPH | power_in | Charge pump switching node. Connect a X5R/X7R 47-nF, VDRAIN-rated ceramic capacitor between CPH and CPL. |+| 2 | VM | power_in | Gate driver power supply input. Connect to VDRAIN or a separate gate driver supply. Use X5R/X7R 0.1-µF, VM-rated ceramic and ≥10-µF local capacitance to GND. |+| 3 | VDRAIN | power_in | High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the external MOSFET drains (motor bus, 9-100 V). |+| 4 | VCP | power_out | Charge pump output. Connect a X5R/X7R 1-µF, 16-V ceramic capacitor between VCP and VDRAIN. |+| 5 | GHA | output | High-side gate driver output, phase A. Connect to the gate of the high-side power MOSFET. |+| 6 | SHA | input | High-side source sense input, phase A. Connect to the high-side power MOSFET source (phase A switch node). |+| 7 | GLA | output | Low-side gate driver output, phase A. Connect to the gate of the low-side power MOSFET. |+| 8 | SLA | input | Low-side source sense input, phase A. Connect to the low-side power MOSFET source (typically PGND or the top of the phase-A shunt). |+| 9 | SLB | input | Low-side source sense input, phase B. Connect to the low-side power MOSFET source (typically PGND or the top of the phase-B shunt). |+| 10 | GLB | output | Low-side gate driver output, phase B. Connect to the gate of the low-side power MOSFET. |+| 11 | SHB | input | High-side source sense input, phase B. Connect to the high-side power MOSFET source (phase B switch node). |+| 12 | GHB | output | High-side gate driver output, phase B. Connect to the gate of the high-side power MOSFET. |+| 13 | GHC | output | High-side gate driver output, phase C. Connect to the gate of the high-side power MOSFET. |+| 14 | SHC | input | High-side source sense input, phase C. Connect to the high-side power MOSFET source (phase C switch node). |+| 15 | GLC | output | Low-side gate driver output, phase C. Connect to the gate of the low-side power MOSFET. |+| 16 | SLC | input | Low-side source sense input, phase C. Connect to the low-side power MOSFET source (typically PGND or the top of the phase-C shunt). |+| 17 | nFAULT | output | Open-drain fault indicator output. Pulled logic low during a fault condition. Requires an external pull-up resistor to a logic supply. |+| 18 | SDO | output | SPI serial data output (open-drain). Data is shifted out on the rising edge of SCLK. Requires an external pull-up resistor. |+| 19 | SDI | input | SPI serial data input (MOSI). Data is captured on the falling edge of SCLK. |+| 20 | SCLK | input | SPI serial clock input. Data is shifted out and captured on the rising and falling edges of this pin. |+| 21 | nSCS | input | SPI chip-select (active low). A logic low on this pin enables serial interface communication. |+| 22 | ENABLE | input | Gate driver enable. Logic low places the device in low-power sleep mode. An 8-40-µs low pulse can be used to reset fault conditions. |+| 23 | INHA | input | High-side gate driver control input, phase A. Controls the output of the high-side gate driver. |+| 24 | INLA | input | Low-side gate driver control input, phase A. Controls the output of the low-side gate driver. |+| 25 | INHB | input | High-side gate driver control input, phase B. Controls the output of the high-side gate driver. |+| 26 | INLB | input | Low-side gate driver control input, phase B. Controls the output of the low-side gate driver. |+| 27 | INHC | input | High-side gate driver control input, phase C. Controls the output of the high-side gate driver. |+| 28 | INLC | input | Low-side gate driver control input, phase C. Controls the output of the low-side gate driver. |+| 29 | DVDD | power_out | 5-V internal regulator output. Connect a X5R/X7R 1-µF, 6.3-V ceramic capacitor between DVDD and GND. Regulator can source up to 10 mA externally. |+| 30 | GND | power_in | Device primary ground. Connect to system ground. |+| 31 | VGLS | power_out | 11-V internal regulator output used for low-side gate supply. Connect a X5R/X7R 1-µF, 16-V ceramic capacitor between VGLS and GND. |+| 32 | CPL | power_in | Charge pump switching node. Connect a X5R/X7R 47-nF, VDRAIN-rated ceramic capacitor between CPH and CPL. |+| 33 | PAD | power_in | Exposed thermal pad. Solder to the PCB ground plane for thermal dissipation and connect to system ground. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-32-EP(5x5) |+| Category | Motor Driver ICs |+| Pins | 33 |++## Ordering variants++Same part, different packaging or reel option.++- `DRV8350SRTVR`+- `DRV8350SRTVT`+- `DRV8350HRTVR`+- `DRV8350HRTVT`+- `DRV8350RSRGZR`+- `DRV8350RSRGZT`+- `DRV8350RHRGZR`+- `DRV8350RHRGZT`+- `DRV8353SRTV`+- `DRV8353HRTV`+- `DRV8353RSRGZ`+- `DRV8353RHRGZ`++## CAD (KiCad official)++- Symbol: `DRV8350SRTVR`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8353) (101 pp, sha256 `4ab34376642b461e`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8350srtvr-datasheet.pdf)