component
DRV8320SRTVR
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Texas Instruments Motor Driver ICs, WQFN-32-EP(5x5). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+304−8@@ -1,13 +1,314 @@ {+ "schema_version": 1,+ "type": "component", "slug": "drv8320srtvr",+ "title": "DRV8320SRTVR",+ "brief": "Texas Instruments Motor Driver ICs, WQFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Texas Instruments Motor Driver ICs, WQFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "power supply chip", "drv8320srtvr" ],+ "component": {+ "mpn": "DRV8320SRTVR",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-32-EP(5x5)",+ "pin_count": 33,+ "category": "Power Supply Chip",+ "subcategory": "Motor Driver ICs",+ "datasheet": "https://www.ti.com/cn/lit/gpn/drv8323r",+ "parts": {+ "symbol": "drv8320srtvr.kicad_sym",+ "footprint": "drv8320srtvr.kicad_mod",+ "model_3d": "drv8320srtvr.glb",+ "model_3d_step": "drv8320srtvr.step",+ "lbr": "drv8320srtvr.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "CPH",+ "type": "passive",+ "description": "Charge pump switching node (high). Connect a 47 nF, X5R/X7R, VM-rated (e.g. 50 V for 24 V systems) ceramic flying capacitor between CPH and CPL."+ },+ {+ "number": "2",+ "name": "VCP",+ "type": "power_out",+ "description": "Charge pump output. Connect a 1 \u00b5F, 25 V, X5R/X7R ceramic capacitor between VCP and VM. Supplies the high-side gate-drive rail."+ },+ {+ "number": "3",+ "name": "VM",+ "type": "power_in",+ "description": "Gate-driver supply input (6 V to 60 V). Tie to motor supply and VDRAIN. Bypass VM to PGND with a \u226510 \u00b5F ceramic (VM-rated) plus a 0.1 \u00b5F X5R/X7R."+ },+ {+ "number": "4",+ "name": "VDRAIN",+ "type": "input",+ "description": "High-side MOSFET drain sense. Connect to the common drain node of the three high-side FETs; used as the VDS-monitor reference."+ },+ {+ "number": "5",+ "name": "GHA",+ "type": "output",+ "description": "High-side phase-A gate drive output. Connect to the gate of the high-side power MOSFET of phase A."+ },+ {+ "number": "6",+ "name": "SHA",+ "type": "bidirectional",+ "description": "High-side phase-A source / switch-node input. Connect to the source of the high-side FET of phase A; serves as VDS monitor and high-side gate-drive current return."+ },+ {+ "number": "7",+ "name": "GLA",+ "type": "output",+ "description": "Low-side phase-A gate drive output. Connect to the gate of the low-side power MOSFET of phase A."+ },+ {+ "number": "8",+ "name": "SLA",+ "type": "input",+ "description": "Low-side phase-A source sense. Connect to the source of the low-side FET of phase A; used as VDS monitor input."+ },+ {+ "number": "9",+ "name": "SLB",+ "type": "input",+ "description": "Low-side phase-B source sense. Connect to the source of the low-side FET of phase B; used as VDS monitor input."+ },+ {+ "number": "10",+ "name": "GLB",+ "type": "output",+ "description": "Low-side phase-B gate drive output. Connect to the gate of the low-side power MOSFET of phase B."+ },+ {+ "number": "11",+ "name": "SHB",+ "type": "bidirectional",+ "description": "High-side phase-B source / switch-node input. Connect to the source of the high-side FET of phase B; VDS monitor and gate-drive current return."+ },+ {+ "number": "12",+ "name": "GHB",+ "type": "output",+ "description": "High-side phase-B gate drive output. Connect to the gate of the high-side power MOSFET of phase B."+ },+ {+ "number": "13",+ "name": "GHC",+ "type": "output",+ "description": "High-side phase-C gate drive output. Connect to the gate of the high-side power MOSFET of phase C."+ },+ {+ "number": "14",+ "name": "SHC",+ "type": "bidirectional",+ "description": "High-side phase-C source / switch-node input. Connect to the source of the high-side FET of phase C; VDS monitor and gate-drive current return."+ },+ {+ "number": "15",+ "name": "GLC",+ "type": "output",+ "description": "Low-side phase-C gate drive output. Connect to the gate of the low-side power MOSFET of phase C."+ },+ {+ "number": "16",+ "name": "SLC",+ "type": "input",+ "description": "Low-side phase-C source sense. Connect to the source of the low-side FET of phase C; VDS monitor input."+ },+ {+ "number": "17",+ "name": "nFAULT",+ "type": "output",+ "description": "Active-low open-drain fault indicator. Pulled low during a fault condition; requires an external pull-up resistor to the logic supply."+ },+ {+ "number": "18",+ "name": "SDO",+ "type": "output",+ "description": "SPI serial data output (open-drain). Data shifts out on the rising edge of SCLK; requires an external pull-up resistor."+ },+ {+ "number": "19",+ "name": "SDI",+ "type": "input",+ "description": "SPI serial data input. Data is captured on the falling edge of SCLK."+ },+ {+ "number": "20",+ "name": "SCLK",+ "type": "input",+ "description": "SPI serial clock input. Data is shifted out on SDO on the rising edge and captured on SDI on the falling edge."+ },+ {+ "number": "21",+ "name": "nSCS",+ "type": "input",+ "description": "SPI chip-select (active low). Logic high disables the serial interface."+ },+ {+ "number": "22",+ "name": "ENABLE",+ "type": "input",+ "description": "Gate-driver enable. Driving low places the device in low-power sleep mode; an 8 \u00b5s to 40 \u00b5s low-going pulse resets fault conditions without entering sleep."+ },+ {+ "number": "23",+ "name": "AGND",+ "type": "power_in",+ "description": "Device analog ground. Connect to system ground; AGND must be externally tied to PGND."+ },+ {+ "number": "24",+ "name": "DVDD",+ "type": "power_out",+ "description": "3.3 V internal LDO output. Bypass DVDD to AGND with a 1 \u00b5F, 6.3 V, X5R/X7R ceramic capacitor. Can source up to 30 mA to external loads."+ },+ {+ "number": "25",+ "name": "INHA",+ "type": "input",+ "description": "High-side gate-driver control input, phase A. In 6\u00d7 PWM mode this pin directly controls the phase-A high-side output."+ },+ {+ "number": "26",+ "name": "INLA",+ "type": "input",+ "description": "Low-side gate-driver control input, phase A. In 6\u00d7 PWM mode this pin directly controls the phase-A low-side output."+ },+ {+ "number": "27",+ "name": "INHB",+ "type": "input",+ "description": "High-side gate-driver control input, phase B. In 6\u00d7 PWM mode this pin directly controls the phase-B high-side output."+ },+ {+ "number": "28",+ "name": "INLB",+ "type": "input",+ "description": "Low-side gate-driver control input, phase B. In 6\u00d7 PWM mode this pin directly controls the phase-B low-side output."+ },+ {+ "number": "29",+ "name": "INHC",+ "type": "input",+ "description": "High-side gate-driver control input, phase C. In 6\u00d7 PWM mode this pin directly controls the phase-C high-side output."+ },+ {+ "number": "30",+ "name": "INLC",+ "type": "input",+ "description": "Low-side gate-driver control input, phase C. In 6\u00d7 PWM mode this pin directly controls the phase-C low-side output."+ },+ {+ "number": "31",+ "name": "PGND",+ "type": "power_in",+ "description": "Device power ground and low-side gate-drive current return. Connect to system ground; PGND must be externally tied to AGND."+ },+ {+ "number": "32",+ "name": "CPL",+ "type": "passive",+ "description": "Charge pump switching node (low). Connect a 47 nF, X5R/X7R, VM-rated ceramic flying capacitor between CPH and CPL."+ },+ {+ "number": "PAD",+ "name": "PAD",+ "type": "power_in",+ "description": "Exposed thermal pad on package underside. Must be soldered to a ground plane for proper heat dissipation and electrical grounding."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/drv8323r",+ "pages": 95,+ "sha256": "98e62c0c61f99755",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Texas Instruments",+ "Package": "WQFN-32-EP(5x5)",+ "Category": "Power Supply Chip",+ "Pins": "33"+ }+ },+ "variants": [+ {+ "mpn": "DRV8320SRTVR",+ "kind": "packaging"+ },+ {+ "mpn": "DRV8320SRTVT",+ "kind": "unknown"+ },+ {+ "mpn": "DRV8320H",+ "kind": "unknown"+ },+ {+ "mpn": "DRV8320RS",+ "kind": "unknown"+ },+ {+ "mpn": "DRV8320RH",+ "kind": "unknown"+ },+ {+ "mpn": "DRV8323H",+ "kind": "unknown"+ },+ {+ "mpn": "DRV8323S",+ "kind": "unknown"+ },+ {+ "mpn": "DRV8323RH",+ "kind": "unknown"+ },+ {+ "mpn": "DRV8323RS",+ "kind": "unknown"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "drv8320srtvr"+ ],+ "discovery_pitch": "DRV8320SRTVR (Texas Instruments) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +326,5 @@ "docs/drv8320srtvr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }