DRV8320SRTVR

@@ -0,0 +1,83 @@+# DRV8320SRTVR++**Texas Instruments** · Motor Driver ICs · WQFN-32-EP(5x5)++DRV8320SRTVR from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CPH | passive | Charge pump switching node (high). Connect a 47 nF, X5R/X7R, VM-rated (e.g. 50 V for 24 V systems) ceramic flying capacitor between CPH and CPL. |+| 2 | VCP | power_out | Charge pump output. Connect a 1 µF, 25 V, X5R/X7R ceramic capacitor between VCP and VM. Supplies the high-side gate-drive rail. |+| 3 | VM | power_in | Gate-driver supply input (6 V to 60 V). Tie to motor supply and VDRAIN. Bypass VM to PGND with a ≥10 µF ceramic (VM-rated) plus a 0.1 µF X5R/X7R. |+| 4 | VDRAIN | input | High-side MOSFET drain sense. Connect to the common drain node of the three high-side FETs; used as the VDS-monitor reference. |+| 5 | GHA | output | High-side phase-A gate drive output. Connect to the gate of the high-side power MOSFET of phase A. |+| 6 | SHA | bidirectional | High-side phase-A source / switch-node input. Connect to the source of the high-side FET of phase A; serves as VDS monitor and high-side gate-drive current return. |+| 7 | GLA | output | Low-side phase-A gate drive output. Connect to the gate of the low-side power MOSFET of phase A. |+| 8 | SLA | input | Low-side phase-A source sense. Connect to the source of the low-side FET of phase A; used as VDS monitor input. |+| 9 | SLB | input | Low-side phase-B source sense. Connect to the source of the low-side FET of phase B; used as VDS monitor input. |+| 10 | GLB | output | Low-side phase-B gate drive output. Connect to the gate of the low-side power MOSFET of phase B. |+| 11 | SHB | bidirectional | High-side phase-B source / switch-node input. Connect to the source of the high-side FET of phase B; VDS monitor and gate-drive current return. |+| 12 | GHB | output | High-side phase-B gate drive output. Connect to the gate of the high-side power MOSFET of phase B. |+| 13 | GHC | output | High-side phase-C gate drive output. Connect to the gate of the high-side power MOSFET of phase C. |+| 14 | SHC | bidirectional | High-side phase-C source / switch-node input. Connect to the source of the high-side FET of phase C; VDS monitor and gate-drive current return. |+| 15 | GLC | output | Low-side phase-C gate drive output. Connect to the gate of the low-side power MOSFET of phase C. |+| 16 | SLC | input | Low-side phase-C source sense. Connect to the source of the low-side FET of phase C; VDS monitor input. |+| 17 | nFAULT | output | Active-low open-drain fault indicator. Pulled low during a fault condition; requires an external pull-up resistor to the logic supply. |+| 18 | SDO | output | SPI serial data output (open-drain). Data shifts out on the rising edge of SCLK; requires an external pull-up resistor. |+| 19 | SDI | input | SPI serial data input. Data is captured on the falling edge of SCLK. |+| 20 | SCLK | input | SPI serial clock input. Data is shifted out on SDO on the rising edge and captured on SDI on the falling edge. |+| 21 | nSCS | input | SPI chip-select (active low). Logic high disables the serial interface. |+| 22 | ENABLE | input | Gate-driver enable. Driving low places the device in low-power sleep mode; an 8 µs to 40 µs low-going pulse resets fault conditions without entering sleep. |+| 23 | AGND | power_in | Device analog ground. Connect to system ground; AGND must be externally tied to PGND. |+| 24 | DVDD | power_out | 3.3 V internal LDO output. Bypass DVDD to AGND with a 1 µF, 6.3 V, X5R/X7R ceramic capacitor. Can source up to 30 mA to external loads. |+| 25 | INHA | input | High-side gate-driver control input, phase A. In 6× PWM mode this pin directly controls the phase-A high-side output. |+| 26 | INLA | input | Low-side gate-driver control input, phase A. In 6× PWM mode this pin directly controls the phase-A low-side output. |+| 27 | INHB | input | High-side gate-driver control input, phase B. In 6× PWM mode this pin directly controls the phase-B high-side output. |+| 28 | INLB | input | Low-side gate-driver control input, phase B. In 6× PWM mode this pin directly controls the phase-B low-side output. |+| 29 | INHC | input | High-side gate-driver control input, phase C. In 6× PWM mode this pin directly controls the phase-C high-side output. |+| 30 | INLC | input | Low-side gate-driver control input, phase C. In 6× PWM mode this pin directly controls the phase-C low-side output. |+| 31 | PGND | power_in | Device power ground and low-side gate-drive current return. Connect to system ground; PGND must be externally tied to AGND. |+| 32 | CPL | passive | Charge pump switching node (low). Connect a 47 nF, X5R/X7R, VM-rated ceramic flying capacitor between CPH and CPL. |+| PAD | PAD | power_in | Exposed thermal pad on package underside. Must be soldered to a ground plane for proper heat dissipation and electrical grounding. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-32-EP(5x5) |+| Category | Power Supply Chip |+| Pins | 33 |++## Ordering variants++Same part, different packaging or reel option.++- `DRV8320SRTVR`+- `DRV8320SRTVT`+- `DRV8320H`+- `DRV8320RS`+- `DRV8320RH`+- `DRV8323H`+- `DRV8323S`+- `DRV8323RH`+- `DRV8323RS`++## CAD (KiCad official)++- Symbol: `DRV8320SRTVR`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8323r) (95 pp, sha256 `98e62c0c61f99755`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8320srtvr-datasheet.pdf)