component
DRV8320SRTVR
Public Made by Adomby adom
Texas Instruments Motor Driver ICs, WQFN-32-EP(5x5). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+14−11@@ -38,13 +38,13 @@ "number": "2", "name": "VCP", "type": "power_out",- "description": "Charge pump output. Connect a 1 \u00b5F, 25 V, X5R/X7R ceramic capacitor between VCP and VM. Supplies the high-side gate-drive rail."+ "description": "Charge pump output. Connect a 1 µF, 25 V, X5R/X7R ceramic capacitor between VCP and VM. Supplies the high-side gate-drive rail." }, { "number": "3", "name": "VM", "type": "power_in",- "description": "Gate-driver supply input (6 V to 60 V). Tie to motor supply and VDRAIN. Bypass VM to PGND with a \u226510 \u00b5F ceramic (VM-rated) plus a 0.1 \u00b5F X5R/X7R."+ "description": "Gate-driver supply input (6 V to 60 V). Tie to motor supply and VDRAIN. Bypass VM to PGND with a ≥10 µF ceramic (VM-rated) plus a 0.1 µF X5R/X7R." }, { "number": "4",@@ -158,7 +158,7 @@ "number": "22", "name": "ENABLE", "type": "input",- "description": "Gate-driver enable. Driving low places the device in low-power sleep mode; an 8 \u00b5s to 40 \u00b5s low-going pulse resets fault conditions without entering sleep."+ "description": "Gate-driver enable. Driving low places the device in low-power sleep mode; an 8 µs to 40 µs low-going pulse resets fault conditions without entering sleep." }, { "number": "23",@@ -170,43 +170,43 @@ "number": "24", "name": "DVDD", "type": "power_out",- "description": "3.3 V internal LDO output. Bypass DVDD to AGND with a 1 \u00b5F, 6.3 V, X5R/X7R ceramic capacitor. Can source up to 30 mA to external loads."+ "description": "3.3 V internal LDO output. Bypass DVDD to AGND with a 1 µF, 6.3 V, X5R/X7R ceramic capacitor. Can source up to 30 mA to external loads." }, { "number": "25", "name": "INHA", "type": "input",- "description": "High-side gate-driver control input, phase A. In 6\u00d7 PWM mode this pin directly controls the phase-A high-side output."+ "description": "High-side gate-driver control input, phase A. In 6× PWM mode this pin directly controls the phase-A high-side output." }, { "number": "26", "name": "INLA", "type": "input",- "description": "Low-side gate-driver control input, phase A. In 6\u00d7 PWM mode this pin directly controls the phase-A low-side output."+ "description": "Low-side gate-driver control input, phase A. In 6× PWM mode this pin directly controls the phase-A low-side output." }, { "number": "27", "name": "INHB", "type": "input",- "description": "High-side gate-driver control input, phase B. In 6\u00d7 PWM mode this pin directly controls the phase-B high-side output."+ "description": "High-side gate-driver control input, phase B. In 6× PWM mode this pin directly controls the phase-B high-side output." }, { "number": "28", "name": "INLB", "type": "input",- "description": "Low-side gate-driver control input, phase B. In 6\u00d7 PWM mode this pin directly controls the phase-B low-side output."+ "description": "Low-side gate-driver control input, phase B. In 6× PWM mode this pin directly controls the phase-B low-side output." }, { "number": "29", "name": "INHC", "type": "input",- "description": "High-side gate-driver control input, phase C. In 6\u00d7 PWM mode this pin directly controls the phase-C high-side output."+ "description": "High-side gate-driver control input, phase C. In 6× PWM mode this pin directly controls the phase-C high-side output." }, { "number": "30", "name": "INLC", "type": "input",- "description": "Low-side gate-driver control input, phase C. In 6\u00d7 PWM mode this pin directly controls the phase-C low-side output."+ "description": "Low-side gate-driver control input, phase C. In 6× PWM mode this pin directly controls the phase-C low-side output." }, { "number": "31",@@ -326,5 +326,8 @@ "docs/drv8320srtvr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }