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DRV8320RSRHAR
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Texas Instruments Brushless DC (BLDC) Motor Driver, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+78@@ -0,0 +1,78 @@+# DRV8320RSRHAR++**Texas Instruments** · Brushless DC (BLDC) Motor Driver · VQFN-40-EP(6x6)++DRV8320RSRHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PGND | power_in | Device power ground; also serves as gate driver return path for low-side MOSFET; must be connected externally to AGND and BGND. |+| 2 | CPL | power_in | Charge pump switch node; connect X5R or X7R 47nF capacitor rated at VM between CPH and CPL. |+| 3 | CPH | power_in | Charge pump switch node; connect X5R or X7R 47nF capacitor rated at VM between CPH and CPL. |+| 4 | VCP | power_in | Charge pump output; connect X5R or X7R 1µF 25V capacitor between VCP and VM. |+| 5 | VM | power_in | Gate driver power supply input (6V to 60V); connect to motor power and VDRAIN with 0.1µF and ≥10µF capacitors to PGND. |+| 6 | VDRAIN | input | High-side MOSFET drain input; connects to common drain point of high-side MOSFETs and provides input to VDS monitor. |+| 7 | GHA | output | High-side gate driver output for phase A; drives high-side power MOSFET gate with up to 1A pull current. |+| 8 | SHA | bidirectional | High-side source pin for phase A; connects to high-side MOSFET source, provides VDS monitor input and gate driver sink current output. |+| 9 | GLA | output | Low-side gate driver output for phase A; drives low-side power MOSFET gate with up to 2A sink current. |+| 10 | SLA | input | Low-side source input for phase A; connects to low-side MOSFET source and provides input to VDS monitor. |+| 11 | SLB | input | Low-side source input for phase B; connects to low-side MOSFET source and provides input to VDS monitor. |+| 12 | GLB | output | Low-side gate driver output for phase B; drives low-side power MOSFET gate with up to 2A sink current. |+| 13 | SHB | bidirectional | High-side source pin for phase B; connects to high-side MOSFET source, provides VDS monitor input and gate driver sink current output. |+| 14 | GHB | output | High-side gate driver output for phase B; drives high-side power MOSFET gate with up to 1A pull current. |+| 15 | GHC | output | High-side gate driver output for phase C; drives high-side power MOSFET gate with up to 1A pull current. |+| 16 | SHC | bidirectional | High-side source pin for phase C; connects to high-side MOSFET source, provides VDS monitor input and gate driver sink current output. |+| 17 | GLC | output | Low-side gate driver output for phase C; drives low-side power MOSFET gate with up to 2A sink current. |+| 18 | SLC | input | Low-side source input for phase C; connects to low-side MOSFET source and provides input to VDS monitor. |+| 19 | GND | power_in | Device ground; connects to system ground. |+| 20 | nFAULT | tri_state | Fault indicator output (open-drain); pulled low during fault conditions, requires external pull-up resistor to VCC. |+| 21 | SDO | tri_state | Serial data output (open-drain); outputs data on SCLK rising edge, requires external pull-up resistor. |+| 22 | SDI | input | Serial data input; data captured on SCLK falling edge for SPI communication. |+| 23 | SCLK | input | Serial clock input; controls timing for serial data transfers on falling and rising edges. |+| 24 | nSCS | input | Serial chip select (active low); logic low on this pin enables SPI interface communication. |+| 25 | ENABLE | input | Gate driver enable (active high); device enters sleep mode when low; 8µs to 40µs pulse resets faults without entering sleep. |+| 26 | AGND | power_in | Device analog ground; must be connected externally to BGND and PGND. |+| 27 | DVDD | power_out | 3.3V internal regulator output (30mA max); connect X5R or X7R 1µF 6.3V capacitor to AGND. |+| 28 | INHA | input | High-side gate driver control input for phase A; controls output in 6x PWM mode. |+| 29 | INLA | input | Low-side gate driver control input for phase A; controls output in 6x PWM mode. |+| 30 | INHB | input | High-side gate driver control input for phase B; controls output in 6x PWM mode. |+| 31 | INLB | input | Low-side gate driver control input for phase B; controls output in 6x PWM mode. |+| 32 | INHC | input | High-side gate driver control input for phase C; controls output in 6x PWM mode. |+| 33 | INLC | input | Low-side gate driver control input for phase C; controls output in 6x PWM mode. |+| 34 | BGND | power_in | Buck regulator ground; must be connected externally to AGND and PGND. |+| 35 | CB | power_in | Buck regulator bootstrap input; connect X5R or X7R 0.1µF 16V capacitor between CB and SW. |+| 36 | SW | output | Buck regulator switch node; connects to inductor, diode, and CB bootstrap capacitor in buck converter topology. |+| 37 | NC | unconnected | No internal connection; can be left floating or connected to system ground. |+| 38 | VIN | power_in | Buck regulator power supply input (4V to 60V); connect X5R or X7R capacitor rated at VM between VIN and BGND. |+| 39 | nSHDN | input | Buck regulator shutdown input (active low); high-voltage tolerant with internal pull-up; pull below 1.25V to disable. |+| 40 | FB | input | Buck regulator feedback input; resistor divider from output sets buck regulator output voltage. |+| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-40-EP(6x6) |+| Category | Motor Driver ICs |+| Pins | 41 |++## CAD (KiCad official)++- Symbol: `DRV8320RSRHAR`+- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`+- 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)+- 3D model files: `drv8320rsrhar-etched.step` / `drv8320rsrhar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8320rsrhar.step` / `drv8320rsrhar.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8323r) (98 pp, sha256 `9c4eee0ec7239000`, retrieved 2026-10-05, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8320rsrhar-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "motor driver ics",+ "drv8320rsrhar",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "drv8320rsrhar.kicad_sym",+ "drv8320rsrhar.kicad_mod",+ "drv8320rsrhar.glb",+ "drv8320rsrhar.step",+ "drv8320rsrhar.lbr",+ "docs/hero.png",+ "docs/drv8320rsrhar-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "drv8320rsrhar-hero.glb",+ "drv8320rsrhar-hero.overlay.json"+ ],+ "component": {+ "mpn": "DRV8320RSRHAR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-40-EP(6x6)",+ "pin_count": 41,+ "category": "Motor Driver ICs",+ "subcategory": "Brushless DC (BLDC) Motor Driver",+ "datasheet": "https://www.ti.com/cn/lit/gpn/drv8323r",+ "parts": {+ "symbol": "drv8320rsrhar.kicad_sym",+ "footprint": "drv8320rsrhar.kicad_mod",+ "model_3d": "drv8320rsrhar-hero.glb",+ "model_3d_plain": "drv8320rsrhar.glb",+ "model_3d_step": "drv8320rsrhar-etched.step",+ "model_3d_step_plain": "drv8320rsrhar.step",+ "lbr": "drv8320rsrhar.lbr"+ },+ "distributor_links": {+ "lcsc": 2150620,+ "digikey": "296-48534-2-ND",+ "mouser": "595-DRV8320RSRHAR"+ },+ "distributor_check": {+ "checked_at": "2026-10-05T23:00:41Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-48534-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-DRV8320RSRHAR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "PGND",+ "type": "power_in",+ "description": "Device power ground; also serves as gate driver return path for low-side MOSFET; must be connected externally to AGND and BGND."+ },+ {+ "number": "2",+ "name": "CPL",+ "type": "power_in",+ "description": "Charge pump switch node; connect X5R or X7R 47nF capacitor rated at VM between CPH and CPL."+ },+ {+ "number": "3",+ "name": "CPH",+ "type": "power_in",+ "description": "Charge pump switch node; connect X5R or X7R 47nF capacitor rated at VM between CPH and CPL."+ },+ {+ "number": "4",+ "name": "VCP",+ "type": "power_in",+ "description": "Charge pump output; connect X5R or X7R 1µF 25V capacitor between VCP and VM."+ },+ {+ "number": "5",+ "name": "VM",+ "type": "power_in",+ "description": "Gate driver power supply input (6V to 60V); connect to motor power and VDRAIN with 0.1µF and ≥10µF capacitors to PGND."+ },+ {+ "number": "6",+ "name": "VDRAIN",+ "type": "input",+ "description": "High-side MOSFET drain input; connects to common drain point of high-side MOSFETs and provides input to VDS monitor."+ },+ {+ "number": "7",+ "name": "GHA",+ "type": "output",+ "description": "High-side gate driver output for phase A; drives high-side power MOSFET gate with up to 1A pull current."+ },+ {+ "number": "8",+ "name": "SHA",+ "type": "bidirectional",+ "description": "High-side source pin for phase A; connects to high-side MOSFET source, provides VDS monitor input and gate driver sink current output."+ },+ {+ "number": "9",+ "name": "GLA",+ "type": "output",+ "description": "Low-side gate driver output for phase A; drives low-side power MOSFET gate with up to 2A sink current."+ },+ {+ "number": "10",+ "name": "SLA",+ "type": "input",+ "description": "Low-side source input for phase A; connects to low-side MOSFET source and provides input to VDS monitor."+ },+ {+ "number": "11",+ "name": "SLB",+ "type": "input",+ "description": "Low-side source input for phase B; connects to low-side MOSFET source and provides input to VDS monitor."+ },+ {+ "number": "12",+ "name": "GLB",+ "type": "output",+ "description": "Low-side gate driver output for phase B; drives low-side power MOSFET gate with up to 2A sink current."+ },+ {+ "number": "13",+ "name": "SHB",+ "type": "bidirectional",+ "description": "High-side source pin for phase B; connects to high-side MOSFET source, provides VDS monitor input and gate driver sink current output."+ },+ {+ "number": "14",+ "name": "GHB",+ "type": "output",+ "description": "High-side gate driver output for phase B; drives high-side power MOSFET gate with up to 1A pull current."+ },+ {+ "number": "15",+ "name": "GHC",+ "type": "output",+ "description": "High-side gate driver output for phase C; drives high-side power MOSFET gate with up to 1A pull current."+ },+ {+ "number": "16",+ "name": "SHC",+ "type": "bidirectional",+ "description": "High-side source pin for phase C; connects to high-side MOSFET source, provides VDS monitor input and gate driver sink current output."+ },+ {+ "number": "17",+ "name": "GLC",+ "type": "output",+ "description": "Low-side gate driver output for phase C; drives low-side power MOSFET gate with up to 2A sink current."+ },+ {+ "number": "18",+ "name": "SLC",+ "type": "input",+ "description": "Low-side source input for phase C; connects to low-side MOSFET source and provides input to VDS monitor."+ },+ {+ "number": "19",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground; connects to system ground."+ },+ {+ "number": "20",+ "name": "nFAULT",+ "type": "tri_state",+ "description": "Fault indicator output (open-drain); pulled low during fault conditions, requires external pull-up resistor to VCC."+ },+ {+ "number": "21",+ "name": "SDO",+ "type": "tri_state",+ "description": "Serial data output (open-drain); outputs data on SCLK rising edge, requires external pull-up resistor."+ },+ {+ "number": "22",+ "name": "SDI",+ "type": "input",+ "description": "Serial data input; data captured on SCLK falling edge for SPI communication."+ },+ {+ "number": "23",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input; controls timing for serial data transfers on falling and rising edges."+ },+ {+ "number": "24",+ "name": "nSCS",+ "type": "input",+ "description": "Serial chip select (active low); logic low on this pin enables SPI interface communication."+ },+ {+ "number": "25",+ "name": "ENABLE",+ "type": "input",+ "description": "Gate driver enable (active high); device enters sleep mode when low; 8µs to 40µs pulse resets faults without entering sleep."+ },+ {+ "number": "26",+ "name": "AGND",+ "type": "power_in",+ "description": "Device analog ground; must be connected externally to BGND and PGND."+ },+ {+ "number": "27",+ "name": "DVDD",+ "type": "power_out",+ "description": "3.3V internal regulator output (30mA max); connect X5R or X7R 1µF 6.3V capacitor to AGND."+ },+ {+ "number": "28",+ "name": "INHA",+ "type": "input",+ "description": "High-side gate driver control input for phase A; controls output in 6x PWM mode."+ },+ {+ "number": "29",+ "name": "INLA",+ "type": "input",+ "description": "Low-side gate driver control input for phase A; controls output in 6x PWM mode."+ },+ {+ "number": "30",+ "name": "INHB",+ "type": "input",+ "description": "High-side gate driver control input for phase B; controls output in 6x PWM mode."+ },+ {+ "number": "31",+ "name": "INLB",+ "type": "input",+ "description": "Low-side gate driver control input for phase B; controls output in 6x PWM mode."+ },+ {+ "number": "32",+ "name": "INHC",+ "type": "input",+ "description": "High-side gate driver control input for phase C; controls output in 6x PWM mode."+ },+ {+ "number": "33",+ "name": "INLC",+ "type": "input",+ "description": "Low-side gate driver control input for phase C; controls output in 6x PWM mode."+ },+ {+ "number": "34",+ "name": "BGND",+ "type": "power_in",+ "description": "Buck regulator ground; must be connected externally to AGND and PGND."+ },+ {+ "number": "35",+ "name": "CB",+ "type": "power_in",+ "description": "Buck regulator bootstrap input; connect X5R or X7R 0.1µF 16V capacitor between CB and SW."+ },+ {+ "number": "36",+ "name": "SW",+ "type": "output",+ "description": "Buck regulator switch node; connects to inductor, diode, and CB bootstrap capacitor in buck converter topology."+ },+ {+ "number": "37",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; can be left floating or connected to system ground."+ },+ {+ "number": "38",+ "name": "VIN",+ "type": "power_in",+ "description": "Buck regulator power supply input (4V to 60V); connect X5R or X7R capacitor rated at VM between VIN and BGND."+ },+ {+ "number": "39",+ "name": "nSHDN",+ "type": "input",+ "description": "Buck regulator shutdown input (active low); high-voltage tolerant with internal pull-up; pull below 1.25V to disable."+ },+ {+ "number": "40",+ "name": "FB",+ "type": "input",+ "description": "Buck regulator feedback input; resistor divider from output sets buck regulator output voltage."+ },+ {+ "number": "41",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin types SHA, SHB, SHC classified as bidirectional (I/O) based on datasheet description indicating ; nFAULT and SDO are open-drain outputs mapped to tri_state type per KiCad ERC classification for open; All power pins (PGND, AGND, BGND, GND) mapped as power_in per KiCad convention; DVDD mapped as power",+ "exposed pad 41 added from the footprint"+ ],+ "pages_sent": 57,+ "cost_usd": 0.5224,+ "at": "2026-10-05T23:00:25"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/drv8323r",+ "pages": 98,+ "sha256": "9c4eee0ec7239000",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}