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DRV8320HRTVR
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Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+70@@ -0,0 +1,70 @@+# DRV8320HRTVR++**Texas Instruments** · Brushless DC (BLDC) Motor Driver · WQFN-32-EP(5x5)++DRV8320HRTVR from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CPH | power_in | Charge pump switching node; connect X5R or X7R 47nF capacitor between CPH and CPL rated for VM voltage with 2× safety margin. |+| 2 | VCP | power_out | Charge pump regulated output (VVM + 11V); connect X5R or X7R 1µF 25V ceramic capacitor between VCP and VM. |+| 3 | VM | power_in | Gate driver power supply input (6V to 60V); connect to motor power and VDRAIN with ≥10µF bulk capacitance and 0.1µF bypass. |+| 4 | VDRAIN | input | High-side MOSFET drain input; connect to common drain point of high-side MOSFETs and provides VDS overvoltage monitoring. |+| 5 | GHA | output | High-side gate driver output phase A; drives high-side MOSFET gate with peak currents up to 1A pull and 2A sink. |+| 6 | SHA | bidirectional | High-side source pin phase A; provides VDS monitoring input and high-side gate driver sink current output for phase A. |+| 7 | GLA | output | Low-side gate driver output phase A; drives low-side MOSFET gate with peak currents up to 1A pull and 2A sink. |+| 8 | SLA | input | Low-side source input phase A; connect to low-side MOSFET source and provides VDS monitoring input. |+| 9 | SLB | input | Low-side source input phase B; connect to low-side MOSFET source and provides VDS monitoring input. |+| 10 | GLB | output | Low-side gate driver output phase B; drives low-side MOSFET gate with peak currents up to 1A pull and 2A sink. |+| 11 | SHB | bidirectional | High-side source pin phase B; provides VDS monitoring input and high-side gate driver sink current output for phase B. |+| 12 | GHB | output | High-side gate driver output phase B; drives high-side MOSFET gate with peak currents up to 1A pull and 2A sink. |+| 13 | GHC | output | High-side gate driver output phase C; drives high-side MOSFET gate with peak currents up to 1A pull and 2A sink. |+| 14 | SHC | bidirectional | High-side source pin phase C; provides VDS monitoring input and high-side gate driver sink current output for phase C. |+| 15 | GLC | output | Low-side gate driver output phase C; drives low-side MOSFET gate with peak currents up to 1A pull and 2A sink. |+| 16 | SLC | input | Low-side source input phase C; connect to low-side MOSFET source and provides VDS monitoring input. |+| 17 | nFAULT | tri_state | Fault indicator open-drain output; pulled low during VM UVLO, charge pump UVLO, VDS OCP, GDF, or thermal shutdown; requires external pull-up resistor. |+| 18 | MODE | input | PWM mode selection input; 4-level input set by external resistor for 6x, 3x, 1x, or independent PWM control modes. |+| 19 | IDRIVE | input | Gate drive current setting; 7-level input set by external resistor selecting peak drive currents from 10mA to 1000mA pull and 20mA to 2000mA sink. |+| 20 | VDS | input | VDS overvoltage trip threshold; 7-level input set by external resistor for VDS protection threshold from 0.06V to 1.88V with adjustable degliching. |+| 21 | NC | unconnected | No internal connection; this pin can be left floating or connected to system ground. |+| 22 | ENABLE | input | Gate driver enable input; logic low enters low-power sleep mode drawing ≤20µA; 8µs to 40µs pulse resets latched faults without sleep. |+| 23 | AGND | power_in | Analog ground; connect to system ground; must be externally connected to PGND to avoid noise coupling. |+| 24 | DVDD | power_out | 3.3V internal regulator output; supplies internal logic and provides 30mA for external loads when bypassed with 1µF 6.3V capacitor. |+| 25 | INHA | input | High-side gate driver control input phase A; in 6x PWM mode controls high-side gate driver output state. |+| 26 | INLA | input | Low-side gate driver control input phase A; in 6x PWM mode controls low-side gate driver output state. |+| 27 | INHB | input | High-side gate driver control input phase B; in 6x PWM mode controls high-side gate driver output state. |+| 28 | INLB | input | Low-side gate driver control input phase B; in 6x PWM mode controls low-side gate driver output state. |+| 29 | INHC | input | High-side gate driver control input phase C; in 6x PWM mode controls high-side gate driver output state. |+| 30 | INLC | input | Low-side gate driver control input phase C; in 6x PWM mode controls low-side gate driver output state. |+| 31 | PGND | power_in | Power ground; also serves as low-side MOSFET gate driver return current path; connect to system ground and externally to AGND. |+| 32 | CPL | power_in | Charge pump negative switching node; connect X5R or X7R 47nF capacitor between CPH and CPL rated for VM voltage with 2× safety margin. |+| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-32-EP(5x5) |+| Category | Motor Driver ICs |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `DRV8320HRTVR`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `drv8320hrtvr-etched.step` / `drv8320hrtvr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8320hrtvr.step` / `drv8320hrtvr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8323r) (95 pp, sha256 `98e62c0c61f99755`, retrieved 2026-09-24, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8320hrtvr-datasheet.pdf)
page.jsonadded+295@@ -0,0 +1,295 @@+{+ "slug": "drv8320hrtvr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "motor driver ics",+ "drv8320hrtvr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "drv8320hrtvr.kicad_sym",+ "drv8320hrtvr.kicad_mod",+ "drv8320hrtvr.glb",+ "drv8320hrtvr.step",+ "drv8320hrtvr.lbr",+ "docs/hero.png",+ "docs/drv8320hrtvr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DRV8320HRTVR",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-32-EP(5x5)",+ "pin_count": 33,+ "category": "Motor Driver ICs",+ "subcategory": "Brushless DC (BLDC) Motor Driver",+ "datasheet": "https://www.ti.com/cn/lit/gpn/drv8323r",+ "parts": {+ "symbol": "drv8320hrtvr.kicad_sym",+ "footprint": "drv8320hrtvr.kicad_mod",+ "model_3d": "drv8320hrtvr-etched.glb",+ "model_3d_plain": "drv8320hrtvr.glb",+ "model_3d_step": "drv8320hrtvr-etched.step",+ "model_3d_step_plain": "drv8320hrtvr.step",+ "lbr": "drv8320hrtvr.lbr"+ },+ "distributor_links": {+ "lcsc": "C701782"+ },+ "pins": [+ {+ "number": "1",+ "name": "CPH",+ "type": "power_in",+ "description": "Charge pump switching node; connect X5R or X7R 47nF capacitor between CPH and CPL rated for VM voltage with 2× safety margin."+ },+ {+ "number": "2",+ "name": "VCP",+ "type": "power_out",+ "description": "Charge pump regulated output (VVM + 11V); connect X5R or X7R 1µF 25V ceramic capacitor between VCP and VM."+ },+ {+ "number": "3",+ "name": "VM",+ "type": "power_in",+ "description": "Gate driver power supply input (6V to 60V); connect to motor power and VDRAIN with ≥10µF bulk capacitance and 0.1µF bypass."+ },+ {+ "number": "4",+ "name": "VDRAIN",+ "type": "input",+ "description": "High-side MOSFET drain input; connect to common drain point of high-side MOSFETs and provides VDS overvoltage monitoring."+ },+ {+ "number": "5",+ "name": "GHA",+ "type": "output",+ "description": "High-side gate driver output phase A; drives high-side MOSFET gate with peak currents up to 1A pull and 2A sink."+ },+ {+ "number": "6",+ "name": "SHA",+ "type": "bidirectional",+ "description": "High-side source pin phase A; provides VDS monitoring input and high-side gate driver sink current output for phase A."+ },+ {+ "number": "7",+ "name": "GLA",+ "type": "output",+ "description": "Low-side gate driver output phase A; drives low-side MOSFET gate with peak currents up to 1A pull and 2A sink."+ },+ {+ "number": "8",+ "name": "SLA",+ "type": "input",+ "description": "Low-side source input phase A; connect to low-side MOSFET source and provides VDS monitoring input."+ },+ {+ "number": "9",+ "name": "SLB",+ "type": "input",+ "description": "Low-side source input phase B; connect to low-side MOSFET source and provides VDS monitoring input."+ },+ {+ "number": "10",+ "name": "GLB",+ "type": "output",+ "description": "Low-side gate driver output phase B; drives low-side MOSFET gate with peak currents up to 1A pull and 2A sink."+ },+ {+ "number": "11",+ "name": "SHB",+ "type": "bidirectional",+ "description": "High-side source pin phase B; provides VDS monitoring input and high-side gate driver sink current output for phase B."+ },+ {+ "number": "12",+ "name": "GHB",+ "type": "output",+ "description": "High-side gate driver output phase B; drives high-side MOSFET gate with peak currents up to 1A pull and 2A sink."+ },+ {+ "number": "13",+ "name": "GHC",+ "type": "output",+ "description": "High-side gate driver output phase C; drives high-side MOSFET gate with peak currents up to 1A pull and 2A sink."+ },+ {+ "number": "14",+ "name": "SHC",+ "type": "bidirectional",+ "description": "High-side source pin phase C; provides VDS monitoring input and high-side gate driver sink current output for phase C."+ },+ {+ "number": "15",+ "name": "GLC",+ "type": "output",+ "description": "Low-side gate driver output phase C; drives low-side MOSFET gate with peak currents up to 1A pull and 2A sink."+ },+ {+ "number": "16",+ "name": "SLC",+ "type": "input",+ "description": "Low-side source input phase C; connect to low-side MOSFET source and provides VDS monitoring input."+ },+ {+ "number": "17",+ "name": "nFAULT",+ "type": "tri_state",+ "description": "Fault indicator open-drain output; pulled low during VM UVLO, charge pump UVLO, VDS OCP, GDF, or thermal shutdown; requires external pull-up resistor."+ },+ {+ "number": "18",+ "name": "MODE",+ "type": "input",+ "description": "PWM mode selection input; 4-level input set by external resistor for 6x, 3x, 1x, or independent PWM control modes."+ },+ {+ "number": "19",+ "name": "IDRIVE",+ "type": "input",+ "description": "Gate drive current setting; 7-level input set by external resistor selecting peak drive currents from 10mA to 1000mA pull and 20mA to 2000mA sink."+ },+ {+ "number": "20",+ "name": "VDS",+ "type": "input",+ "description": "VDS overvoltage trip threshold; 7-level input set by external resistor for VDS protection threshold from 0.06V to 1.88V with adjustable degliching."+ },+ {+ "number": "21",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; this pin can be left floating or connected to system ground."+ },+ {+ "number": "22",+ "name": "ENABLE",+ "type": "input",+ "description": "Gate driver enable input; logic low enters low-power sleep mode drawing ≤20µA; 8µs to 40µs pulse resets latched faults without sleep."+ },+ {+ "number": "23",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; connect to system ground; must be externally connected to PGND to avoid noise coupling."+ },+ {+ "number": "24",+ "name": "DVDD",+ "type": "power_out",+ "description": "3.3V internal regulator output; supplies internal logic and provides 30mA for external loads when bypassed with 1µF 6.3V capacitor."+ },+ {+ "number": "25",+ "name": "INHA",+ "type": "input",+ "description": "High-side gate driver control input phase A; in 6x PWM mode controls high-side gate driver output state."+ },+ {+ "number": "26",+ "name": "INLA",+ "type": "input",+ "description": "Low-side gate driver control input phase A; in 6x PWM mode controls low-side gate driver output state."+ },+ {+ "number": "27",+ "name": "INHB",+ "type": "input",+ "description": "High-side gate driver control input phase B; in 6x PWM mode controls high-side gate driver output state."+ },+ {+ "number": "28",+ "name": "INLB",+ "type": "input",+ "description": "Low-side gate driver control input phase B; in 6x PWM mode controls low-side gate driver output state."+ },+ {+ "number": "29",+ "name": "INHC",+ "type": "input",+ "description": "High-side gate driver control input phase C; in 6x PWM mode controls high-side gate driver output state."+ },+ {+ "number": "30",+ "name": "INLC",+ "type": "input",+ "description": "Low-side gate driver control input phase C; in 6x PWM mode controls low-side gate driver output state."+ },+ {+ "number": "31",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground; also serves as low-side MOSFET gate driver return current path; connect to system ground and externally to AGND."+ },+ {+ "number": "32",+ "name": "CPL",+ "type": "power_in",+ "description": "Charge pump negative switching node; connect X5R or X7R 47nF capacitor between CPH and CPL rated for VM voltage with 2× safety margin."+ },+ {+ "number": "33",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The DRV8320HRTVR MPN is the hardware interface variant (H suffix) which uses fixed resistor-programm",+ "exposed pad 33 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 95,+ "cost_usd": 1.1173,+ "at": "2026-09-24T06:29:20"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/drv8323r",+ "pages": 95,+ "sha256": "98e62c0c61f99755",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}