component
DRV8320HRTVR
Public Made by Adomby adom
Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
drv8320hrtvr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
2 files changed
+90−10
package.json+48−8@@ -53,19 +53,19 @@ "number": "1", "name": "CPH", "type": "power_in",- "description": "Charge pump switching node; connect X5R or X7R 47nF capacitor between CPH and CPL rated for VM voltage with 2\u00d7 safety margin."+ "description": "Charge pump switching node; connect X5R or X7R 47nF capacitor between CPH and CPL rated for VM voltage with 2× safety margin." }, { "number": "2", "name": "VCP", "type": "power_out",- "description": "Charge pump regulated output (VVM + 11V); connect X5R or X7R 1\u00b5F 25V ceramic capacitor between VCP and VM."+ "description": "Charge pump regulated output (VVM + 11V); connect X5R or X7R 1µF 25V ceramic capacitor between VCP and VM." }, { "number": "3", "name": "VM", "type": "power_in",- "description": "Gate driver power supply input (6V to 60V); connect to motor power and VDRAIN with \u226510\u00b5F bulk capacitance and 0.1\u00b5F bypass."+ "description": "Gate driver power supply input (6V to 60V); connect to motor power and VDRAIN with ≥10µF bulk capacitance and 0.1µF bypass." }, { "number": "4",@@ -179,7 +179,7 @@ "number": "22", "name": "ENABLE", "type": "input",- "description": "Gate driver enable input; logic low enters low-power sleep mode drawing \u226420\u00b5A; 8\u00b5s to 40\u00b5s pulse resets latched faults without sleep."+ "description": "Gate driver enable input; logic low enters low-power sleep mode drawing ≤20µA; 8µs to 40µs pulse resets latched faults without sleep." }, { "number": "23",@@ -191,7 +191,7 @@ "number": "24", "name": "DVDD", "type": "power_out",- "description": "3.3V internal regulator output; supplies internal logic and provides 30mA for external loads when bypassed with 1\u00b5F 6.3V capacitor."+ "description": "3.3V internal regulator output; supplies internal logic and provides 30mA for external loads when bypassed with 1µF 6.3V capacitor." }, { "number": "25",@@ -239,7 +239,7 @@ "number": "32", "name": "CPL", "type": "power_in",- "description": "Charge pump negative switching node; connect X5R or X7R 47nF capacitor between CPH and CPL rated for VM voltage with 2\u00d7 safety margin."+ "description": "Charge pump negative switching node; connect X5R or X7R 47nF capacitor between CPH and CPL rated for VM voltage with 2× safety margin." }, { "number": "33",@@ -284,6 +284,46 @@ "viewers": { "symbol": "viewers/symbol.html", "footprint": "viewers/footprint.html"- }+ },+ "models_3d": [+ {+ "file": "drv8320hrtvr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5.0,+ 5.0,+ 0.875+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "5fa713ea46b36980895812ed853577889b7cb06d275041a39b99bc0be305dc79",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "drv8320hrtvr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5.0,+ 5.0,+ 0.875+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "86faf647883e80a2923e3fd4b8c7c150f732e471f2344c69510a49c7918b2027",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ] }-}+}
page.json+42−2@@ -269,7 +269,47 @@ "viewers": { "symbol": "viewers/symbol.html", "footprint": "viewers/footprint.html"- }+ },+ "models_3d": [+ {+ "file": "drv8320hrtvr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5.0,+ 5.0,+ 0.875+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "5fa713ea46b36980895812ed853577889b7cb06d275041a39b99bc0be305dc79",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "drv8320hrtvr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5.0,+ 5.0,+ 0.875+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "86faf647883e80a2923e3fd4b8c7c150f732e471f2344c69510a49c7918b2027",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ] }, "metadata": { "specs": {@@ -316,4 +356,4 @@ "visibility": { "public": true }-}+}