dp83tc812rrharq1

@@ -0,0 +1,78 @@+# DP83TC812RRHARQ1++**Texas Instruments** · Ethernet Transceivers · VQFN-36(6x6)++DP83TC812RRHARQ1 from Texas Instruments, in a VQFN-36(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | MDC | input | Management Data Clock. Synchronous clock for the MDIO serial management interface, up to 20 MHz; may be asynchronous to MAC TX/RX clocks. No minimum clock rate. |+| 2 | INT_N | bidirectional | Active-LOW interrupt output with weak internal pull-up (open drain by default). Asserted LOW on interrupt; register access required to enable triggers and clear events. Can be configured as active-HIGH or as a power-down control input via register 0x0011. |+| 3 | RESET_N | input | Active-LOW reset input with internal pull-up. Asserting LOW for at least 1 µs forces a full reset; all internal registers reinitialize to defaults and bootstrap pins are resampled on deassertion. |+| 4 | XO | output | Reference Clock Output for crystal oscillator use only. Must be left floating when a CMOS-level oscillator is fed into XI. |+| 5 | XI | input | Reference Clock Input. 25 MHz crystal or CMOS oscillator for MII/RGMII/RMII Master modes; 50 MHz CMOS oscillator required in RMII Slave mode. Also supports daisy-chained clock in from another PHY/MAC. |+| 6 | LED_1/GPIO_1 | bidirectional | Link Status and TX/RX BLINK activity LED with 9 kΩ internal pull-down (bootstrap). Can be reprogrammed as GPIO, LED, or clock output via strap/register. |+| 7 | VSLEEP | power_in | 3.3 V sleep-domain supply used to keep the wake circuitry alive in TC-10 sleep. Decouple with 0.1 µF ceramic. |+| 8 | WAKE | bidirectional | Active-HIGH TC-10 sleep wake input/output with 455 kΩ internal pull-down. Driving HIGH wakes the PHY from TC-10 SLEEP; a 10 kΩ external pull-down is recommended when TC-10 is used. Can also emit a wake pulse to wake other PHYs. |+| 9 | NC | unconnected | No connection. May be left floating; connecting to any signal has no effect on PHY performance. |+| 10 | INH | output | Active-HIGH open-drain-capable output used to enable an external regulator. Hi-Z during TC-10 SLEEP; HIGH in all other PHY states. Use a 2 kΩ-10 kΩ pull-down when implementing TC-10 (single pull-down shared if multiple PHYs share INH). |+| 11 | VDDA | power_in | 3.3 V analog/core supply. Decouple with 0.47 µF and 0.01 µF ceramics; optional ferrite bead may be added. |+| 12 | TRD_P | bidirectional | MDI differential transmit/receive positive line. Bidirectional 100BASE-T1 (IEEE 802.3bw) single-pair signaling. Pair with TRD_M through the CMC and CM-termination network to the automotive connector. |+| 13 | TRD_M | bidirectional | MDI differential transmit/receive negative line. Bidirectional 100BASE-T1 (IEEE 802.3bw) single-pair signaling. Pair with TRD_P. |+| 14 | RX_ER | output | Receive Error output for MII and RMII modes. Asserted HIGH synchronous to RX_CLK (MII) or the reference clock (RMII) when an error symbol is detected in a received packet. Unused in RGMII and SGMII modes (PHY corrupts data on receive errors automatically). |+| 15 | RX_DV/CRS_DV/RX_CTRL | output | MII Receive Data Valid, RMII Carrier Sense/Data Valid, or RGMII Receive Control depending on MAC-interface mode. Combines valid + error indication in RGMII (RX_DV on rising edge of RX_CLK, RX_ER on falling edge). Unused in SGMII mode. |+| 16 | CLKOUT/GPIO_2 | bidirectional | 25 MHz reference clock output; also usable as LED or GPIO via strap/register. Program register 0x045F=0x000F and 0x0453=0x0003 to disable switching on this pin. |+| 17 | GND_ESC | passive | Optional Ground Escape. May be tied to ground to improve PCB layout, but is NOT a substitute for the DAP ground connection. Leave unconnected if unused. |+| 18 | GND_ESC | passive | Optional Ground Escape. May be tied to ground to improve PCB layout, but is NOT a substitute for the DAP ground connection. Leave unconnected if unused. |+| 19 | DNC | unconnected | Do Not Connect. Leave floating. |+| 20 | DNC | unconnected | Do Not Connect. Leave floating. |+| 21 | NC | unconnected | No connection. May be left floating; connecting to any signal has no effect on PHY performance. |+| 22 | VDDMAC | power_in | Optional MAC-interface supply of 1.8 V, 2.5 V, or 3.3 V; may be at a different voltage level than the other I/O pins. Decouple with 0.47 µF and 0.01 µF ceramics and a ferrite bead. When not needed separately, tie to VDDIO through a shared ferrite bead (0.47 µF must remain local to VDDMAC). |+| 23 | RX_D3 | output | MII Receive Data bit 3, valid on the rising edge of RX_CLK. Not used in RMII mode (unless bootstrapped to RMII Master, in which case this pin outputs a 50 MHz reference clock to the MAC). Not used in RGMII mode. |+| 24 | RX_D2 | output | MII Receive Data bit 2, valid on the rising edge of RX_CLK. Not used in RMII or RGMII modes. |+| 25 | RX_D1 | output | Receive Data bit 1, valid on the rising edge of RX_CLK in MII and RMII modes. Not used in RGMII mode. |+| 26 | RX_D0 | output | Receive Data bit 0, valid on the rising edge of RX_CLK in MII and RMII modes. Not used in RGMII mode. |+| 27 | RX_CLK | output | Receive Clock. Provides a 25 MHz reference clock in MII and RGMII modes. Unused in RMII and SGMII modes. |+| 28 | TX_CLK | bidirectional | Transmit Clock. In MII mode this is a 25 MHz output with a 50 Ω driver, phase-referenced to the reference clock. In RGMII mode the MAC drives a 25 MHz clock into this pin (not required to be phase-referenced unless synchronous RGMII is enabled). Unused in RMII and SGMII modes. |+| 29 | TX_EN/TX_CTRL | input | MII/RMII Transmit Enable or RGMII Transmit Control. In MII, indicates valid data on TX_D[3:0] prior to the rising edge of TX_CLK; in RMII, prior to the rising edge of the reference clock. In RGMII, combines TX_EN (rising edge of TX_CLK) and TX_ER (falling edge). Unused in SGMII mode. |+| 30 | TX_D3 | input | MII Transmit Data bit 3, sampled on the rising edge of TX_CLK. Not used in RMII or RGMII modes. |+| 31 | TX_D2 | input | MII Transmit Data bit 2, sampled on the rising edge of TX_CLK. Not used in RMII or RGMII modes. |+| 32 | TX_D1 | input | Transmit Data bit 1, sampled on the rising edge of TX_CLK (MII) or the reference clock (RMII). Not used in RGMII mode. |+| 33 | TX_D0 | input | Transmit Data bit 0, sampled on the rising edge of TX_CLK (MII) or the reference clock (RMII). Not used in RGMII mode. |+| 34 | VDDIO | power_in | Digital I/O supply of 1.8 V, 2.5 V, or 3.3 V. Decouple with a ferrite bead plus 0.47 µF and 0.01 µF ceramics. |+| 35 | LED_0/GPIO_0 | bidirectional | Link Status LED with 9 kΩ internal pull-down (bootstrap). Can also be used as a GPIO or clock output via register selection. |+| 36 | MDIO | bidirectional | Management Data Input/Output. Open-drain bidirectional serial management line sourced by the management station or the PHY. Requires an external pull-up resistor between 2.2 kΩ and 9 kΩ (single shared pull-up on a bus with multiple PHYs). |+| DAP | GND | power_in | Die Attach Pad ground. Must always be connected to power ground. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-36(6x6) |+| Category | Interface |+| Pins | 37 |++## Ordering variants++- `DP83TC812RRHARQ1`+- `DP83TC812RRHARQ1 (S-Q1 orderable base)`++## CAD (KiCad official)++- Symbol: `DP83TC812RRHARQ1`+- Footprint: `Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm`+- 3D model: VQFN-36(6x6) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](docs/dp83tc812rrharq1-datasheet.pdf) (198 pp, sha256 `e9c0b33b38d7d215`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dp83tc812rrharq1-datasheet.pdf)

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