dp83tc812rrharq1

@@ -33,5 +33,253 @@   "author": {     "name": "Ray",     "email": "[email protected]"+  },+  "component": {+    "mpn": "DP83TC812RRHARQ1",+    "manufacturer": "Texas Instruments",+    "package": "VQFN-36(6x6)",+    "pin_count": 37,+    "category": "Ethernet Transceivers",+    "parts": {+      "symbol": "dp83tc812rrharq1.kicad_sym",+      "footprint": "dp83tc812rrharq1.kicad_mod",+      "model_3d": "dp83tc812rrharq1-etched.glb",+      "model_3d_plain": "dp83tc812rrharq1.glb",+      "model_3d_step": "dp83tc812rrharq1-etched.step",+      "model_3d_step_plain": "dp83tc812rrharq1.step",+      "lbr": "dp83tc812rrharq1.lbr"+    },+    "pins": [+      {+        "number": "1",+        "name": "MDC",+        "type": "input",+        "description": "Management Data Clock. Synchronous clock for the MDIO serial management interface, up to 20 MHz; may be asynchronous to MAC TX/RX clocks. No minimum clock rate."+      },+      {+        "number": "2",+        "name": "INT_N",+        "type": "bidirectional",+        "description": "Active-LOW interrupt output with weak internal pull-up (open drain by default). Asserted LOW on interrupt; register access required to enable triggers and clear events. Can be configured as active-HIGH or as a power-down control input via register 0x0011."+      },+      {+        "number": "3",+        "name": "RESET_N",+        "type": "input",+        "description": "Active-LOW reset input with internal pull-up. Asserting LOW for at least 1 µs forces a full reset; all internal registers reinitialize to defaults and bootstrap pins are resampled on deassertion."+      },+      {+        "number": "4",+        "name": "XO",+        "type": "output",+        "description": "Reference Clock Output for crystal oscillator use only. Must be left floating when a CMOS-level oscillator is fed into XI."+      },+      {+        "number": "5",+        "name": "XI",+        "type": "input",+        "description": "Reference Clock Input. 25 MHz crystal or CMOS oscillator for MII/RGMII/RMII Master modes; 50 MHz CMOS oscillator required in RMII Slave mode. Also supports daisy-chained clock in from another PHY/MAC."+      },+      {+        "number": "6",+        "name": "LED_1/GPIO_1",+        "type": "bidirectional",+        "description": "Link Status and TX/RX BLINK activity LED with 9 kΩ internal pull-down (bootstrap). Can be reprogrammed as GPIO, LED, or clock output via strap/register."+      },+      {+        "number": "7",+        "name": "VSLEEP",+        "type": "power_in",+        "description": "3.3 V sleep-domain supply used to keep the wake circuitry alive in TC-10 sleep. Decouple with 0.1 µF ceramic."+      },+      {+        "number": "8",+        "name": "WAKE",+        "type": "bidirectional",+        "description": "Active-HIGH TC-10 sleep wake input/output with 455 kΩ internal pull-down. Driving HIGH wakes the PHY from TC-10 SLEEP; a 10 kΩ external pull-down is recommended when TC-10 is used. Can also emit a wake pulse to wake other PHYs."+      },+      {+        "number": "9",+        "name": "NC",+        "type": "unconnected",+        "description": "No connection. May be left floating; connecting to any signal has no effect on PHY performance."+      },+      {+        "number": "10",+        "name": "INH",+        "type": "output",+        "description": "Active-HIGH open-drain-capable output used to enable an external regulator. Hi-Z during TC-10 SLEEP; HIGH in all other PHY states. Use a 2 kΩ-10 kΩ pull-down when implementing TC-10 (single pull-down shared if multiple PHYs share INH)."+      },+      {+        "number": "11",+        "name": "VDDA",+        "type": "power_in",+        "description": "3.3 V analog/core supply. Decouple with 0.47 µF and 0.01 µF ceramics; optional ferrite bead may be added."+      },+      {+        "number": "12",+        "name": "TRD_P",+        "type": "bidirectional",+        "description": "MDI differential transmit/receive positive line. Bidirectional 100BASE-T1 (IEEE 802.3bw) single-pair signaling. Pair with TRD_M through the CMC and CM-termination network to the automotive connector."+      },+      {+        "number": "13",+        "name": "TRD_M",+        "type": "bidirectional",+        "description": "MDI differential transmit/receive negative line. Bidirectional 100BASE-T1 (IEEE 802.3bw) single-pair signaling. Pair with TRD_P."+      },+      {+        "number": "14",+        "name": "RX_ER",+        "type": "output",+        "description": "Receive Error output for MII and RMII modes. Asserted HIGH synchronous to RX_CLK (MII) or the reference clock (RMII) when an error symbol is detected in a received packet. Unused in RGMII and SGMII modes (PHY corrupts data on receive errors automatically)."+      },+      {+        "number": "15",+        "name": "RX_DV/CRS_DV/RX_CTRL",+        "type": "output",+        "description": "MII Receive Data Valid, RMII Carrier Sense/Data Valid, or RGMII Receive Control depending on MAC-interface mode. Combines valid + error indication in RGMII (RX_DV on rising edge of RX_CLK, RX_ER on falling edge). Unused in SGMII mode."+      },+      {+        "number": "16",+        "name": "CLKOUT/GPIO_2",+        "type": "bidirectional",+        "description": "25 MHz reference clock output; also usable as LED or GPIO via strap/register. Program register 0x045F=0x000F and 0x0453=0x0003 to disable switching on this pin."+      },+      {+        "number": "17",+        "name": "GND_ESC",+        "type": "passive",+        "description": "Optional Ground Escape. May be tied to ground to improve PCB layout, but is NOT a substitute for the DAP ground connection. Leave unconnected if unused."+      },+      {+        "number": "18",+        "name": "GND_ESC",+        "type": "passive",+        "description": "Optional Ground Escape. May be tied to ground to improve PCB layout, but is NOT a substitute for the DAP ground connection. Leave unconnected if unused."+      },+      {+        "number": "19",+        "name": "DNC",+        "type": "unconnected",+        "description": "Do Not Connect. Leave floating."+      },+      {+        "number": "20",+        "name": "DNC",+        "type": "unconnected",+        "description": "Do Not Connect. Leave floating."+      },+      {+        "number": "21",+        "name": "NC",+        "type": "unconnected",+        "description": "No connection. May be left floating; connecting to any signal has no effect on PHY performance."+      },+      {+        "number": "22",+        "name": "VDDMAC",+        "type": "power_in",+        "description": "Optional MAC-interface supply of 1.8 V, 2.5 V, or 3.3 V; may be at a different voltage level than the other I/O pins. Decouple with 0.47 µF and 0.01 µF ceramics and a ferrite bead. When not needed separately, tie to VDDIO through a shared ferrite bead (0.47 µF must remain local to VDDMAC)."+      },+      {+        "number": "23",+        "name": "RX_D3",+        "type": "output",+        "description": "MII Receive Data bit 3, valid on the rising edge of RX_CLK. Not used in RMII mode (unless bootstrapped to RMII Master, in which case this pin outputs a 50 MHz reference clock to the MAC). Not used in RGMII mode."+      },+      {+        "number": "24",+        "name": "RX_D2",+        "type": "output",+        "description": "MII Receive Data bit 2, valid on the rising edge of RX_CLK. Not used in RMII or RGMII modes."+      },+      {+        "number": "25",+        "name": "RX_D1",+        "type": "output",+        "description": "Receive Data bit 1, valid on the rising edge of RX_CLK in MII and RMII modes. Not used in RGMII mode."+      },+      {+        "number": "26",+        "name": "RX_D0",+        "type": "output",+        "description": "Receive Data bit 0, valid on the rising edge of RX_CLK in MII and RMII modes. Not used in RGMII mode."+      },+      {+        "number": "27",+        "name": "RX_CLK",+        "type": "output",+        "description": "Receive Clock. Provides a 25 MHz reference clock in MII and RGMII modes. Unused in RMII and SGMII modes."+      },+      {+        "number": "28",+        "name": "TX_CLK",+        "type": "bidirectional",+        "description": "Transmit Clock. In MII mode this is a 25 MHz output with a 50 Ω driver, phase-referenced to the reference clock. In RGMII mode the MAC drives a 25 MHz clock into this pin (not required to be phase-referenced unless synchronous RGMII is enabled). Unused in RMII and SGMII modes."+      },+      {+        "number": "29",+        "name": "TX_EN/TX_CTRL",+        "type": "input",+        "description": "MII/RMII Transmit Enable or RGMII Transmit Control. In MII, indicates valid data on TX_D[3:0] prior to the rising edge of TX_CLK; in RMII, prior to the rising edge of the reference clock. In RGMII, combines TX_EN (rising edge of TX_CLK) and TX_ER (falling edge). Unused in SGMII mode."+      },+      {+        "number": "30",+        "name": "TX_D3",+        "type": "input",+        "description": "MII Transmit Data bit 3, sampled on the rising edge of TX_CLK. Not used in RMII or RGMII modes."+      },+      {+        "number": "31",+        "name": "TX_D2",+        "type": "input",+        "description": "MII Transmit Data bit 2, sampled on the rising edge of TX_CLK. Not used in RMII or RGMII modes."+      },+      {+        "number": "32",+        "name": "TX_D1",+        "type": "input",+        "description": "Transmit Data bit 1, sampled on the rising edge of TX_CLK (MII) or the reference clock (RMII). Not used in RGMII mode."+      },+      {+        "number": "33",+        "name": "TX_D0",+        "type": "input",+        "description": "Transmit Data bit 0, sampled on the rising edge of TX_CLK (MII) or the reference clock (RMII). Not used in RGMII mode."+      },+      {+        "number": "34",+        "name": "VDDIO",+        "type": "power_in",+        "description": "Digital I/O supply of 1.8 V, 2.5 V, or 3.3 V. Decouple with a ferrite bead plus 0.47 µF and 0.01 µF ceramics."+      },+      {+        "number": "35",+        "name": "LED_0/GPIO_0",+        "type": "bidirectional",+        "description": "Link Status LED with 9 kΩ internal pull-down (bootstrap). Can also be used as a GPIO or clock output via register selection."+      },+      {+        "number": "36",+        "name": "MDIO",+        "type": "bidirectional",+        "description": "Management Data Input/Output. Open-drain bidirectional serial management line sourced by the management station or the PHY. Requires an external pull-up resistor between 2.2 kΩ and 9 kΩ (single shared pull-up on a bus with multiple PHYs)."+      },+      {+        "number": "DAP",+        "name": "GND",+        "type": "power_in",+        "description": "Die Attach Pad ground. Must always be connected to power ground.",+        "thermal_pad": true+      }+    ],+    "provenance": {+      "rebuilt": "component block rebuilt 2026-10-05 from this page's own README pinout table and .kicad_sym (pins cross-checked), no re-extraction"+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }   }-}\ No newline at end of file+}