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DP83869HMRGZT
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Texas Instruments Ethernet Transceivers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+86@@ -0,0 +1,86 @@+# DP83869HMRGZT++**Texas Instruments** · Ethernet Transceivers · VQFN-48-EP(7x7)++DP83869HMRGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | TD_P_A | bidirectional | Differential transmit and receive signal for channel A, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor. |+| 2 | TD_M_A | bidirectional | Differential transmit and receive signal for channel A, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor. |+| 3 | VDDA2P5 | power_in | 2.5V analog power supply (±5%) requiring 1µF and 0.1µF capacitors to ground at each pin. |+| 4 | TD_P_B | bidirectional | Differential transmit and receive signal for channel B, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor. |+| 5 | TD_M_B | bidirectional | Differential transmit and receive signal for channel B, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor. |+| 6 | VDD1P1 | power_in | 1.1V digital power supply (±10%) requiring 1µF and 0.1µF capacitors to ground at each pin. |+| 7 | TD_P_C | bidirectional | Differential transmit and receive signal for channel C, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor. |+| 8 | TD_M_C | bidirectional | Differential transmit and receive signal for channel C, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor. |+| 9 | VDDA2P5 | power_in | 2.5V analog power supply (±5%) requiring 1µF and 0.1µF capacitors to ground at each pin. |+| 10 | TD_P_D | bidirectional | Differential transmit and receive signal for channel D, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor. |+| 11 | TD_M_D | bidirectional | Differential transmit and receive signal for channel D, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor. |+| 12 | RBIAS | passive | Bias resistor connection requiring external 11kΩ ±1% resistor connected to ground for impedance matching. |+| 13 | VDDA1P8_1 | power_in | 1.8V analog power supply (±5%) for triple power mode, no connection required in dual power mode and must remain unconnected when unused. |+| 14 | SON | output | Differential SGMII or fiber data output providing LVDS signal AC-coupled via 0.1µF capacitor from PHY to MAC or transceiver. |+| 15 | SOP | output | Differential SGMII or fiber data output providing LVDS signal AC-coupled via 0.1µF capacitor from PHY to MAC or transceiver. |+| 16 | SIP | input | Differential SGMII or fiber data input receiving LVDS signal AC-coupled via 0.1µF capacitor from MAC or transceiver to PHY. |+| 17 | SIN | input | Differential SGMII or fiber data input receiving LVDS signal AC-coupled via 0.1µF capacitor from MAC or transceiver to PHY. |+| 18 | VDDIO | power_in | I/O power supply selectable as 1.8V (±5%), 2.5V (±5%), or 3.3V (±5%) requiring 1µF and 0.1µF capacitors to ground. |+| 19 | XO | output | Crystal oscillator output for 25MHz crystal secondary connection, must remain floating if external clock oscillator is used. |+| 20 | XI | input | Crystal oscillator input for 25MHz reference clock from crystal or external CMOS oscillator. |+| 21 | JTAG_CLK/TX_ER | input | JTAG test clock input per IEEE 1149.1 standard or MII transmit error signal in 100M mode with internal weak pull-up. |+| 22 | JTAG_TDO/GPIO_1 | output | JTAG test data output per IEEE 1149.1 standard or configurable GPIO output controlled by GPIO_MUX_CTRL register. |+| 23 | JTAG_TMS | input | JTAG test mode select input per IEEE 1149.1 standard for TAP controller with internal weak pull-up. |+| 24 | JTAG_TDI/SD | input | JTAG test data input per IEEE 1149.1 standard or active-low signal detect input for 1000Base-X and 100Base-FX fiber modes with weak pull-up. |+| 25 | TX_D3 | input | Transmit data bit 3 synchronized with transmit clock for RGMII and MII modes with internal weak pull-down. |+| 26 | TX_D2 | input | Transmit data bit 2 synchronized with transmit clock for RGMII and MII modes with internal weak pull-down. |+| 27 | TX_D1 | input | Transmit data bit 1 synchronized with transmit clock for RGMII and MII modes with internal weak pull-down. |+| 28 | TX_D0 | input | Transmit data bit 0 synchronized with transmit clock for RGMII and MII modes with internal weak pull-down. |+| 29 | GTX_CLK/TX_CLK | bidirectional | RGMII transmit clock input at 125MHz or MII transmit clock output at 25MHz (100Mbps) or 2.5MHz (10Mbps) with mode-dependent direction. |+| 30 | VDDIO | power_in | I/O power supply selectable as 1.8V (±5%), 2.5V (±5%), or 3.3V (±5%) requiring 1µF and 0.1µF capacitors to ground. |+| 31 | VDD1P1 | power_in | 1.1V digital power supply (±10%) requiring 1µF and 0.1µF capacitors to ground at each pin. |+| 32 | RX_CLK | output | Recovered receive clock output providing 125MHz for 1000Mbps RGMII mode and 25MHz for 100Mbps or 2.5MHz for 10Mbps modes. |+| 33 | RX_D0 | output | Receive data bit 0 from PHY to MAC synchronized with RX_CLK in RGMII and MII modes. |+| 34 | RX_D1 | output | Receive data bit 1 from PHY to MAC synchronized with RX_CLK in RGMII and MII modes. |+| 35 | RX_D2 | output | Receive data bit 2 from PHY to MAC synchronized with RX_CLK in RGMII and MII modes. |+| 36 | RX_D3 | output | Receive data bit 3 from PHY to MAC synchronized with RX_CLK in RGMII and MII modes. |+| 37 | TX_CTRL/TX_EN | input | Transmit control in RGMII mode combining TX_EN and TX_ER on clock edges, or transmit enable in MII mode with internal weak pull-down. |+| 38 | RX_CTRL/RX_DV | output | Receive control in RGMII mode combining RX_DV and RX_ER on clock edges, or receive data valid in MII mode. |+| 39 | VDD1P1 | power_in | 1.1V digital power supply (±10%) requiring 1µF and 0.1µF capacitors to ground at each pin. |+| 40 | CLK_OUT | output | Programmable clock output providing 25MHz default or configurable to 125/5MHz recovery clock per I/O configuration register. |+| 41 | MDIO | bidirectional | Management data I/O for serial MDIO interface, open-drain requiring external 1.5kΩ pull-up resistor to VDDIO. |+| 42 | MDC | input | Management data clock for MDIO synchronous interface operating up to 25MHz maximum frequency. |+| 43 | RESET_N | input | Active-low reset input for device initialization requiring 100Ω series resistor and 47µF capacitor to ground. |+| 44 | INT_N/PWDN_N | bidirectional | Configurable as active-low power down input or open-drain interrupt output per register control with internal pull-up. |+| 45 | LED_2/GPIO_0 | bidirectional | LED output or configurable GPIO output controlled by GPIO_MUX_CTRL register with polarity set by strap configuration. |+| 46 | LED_1/RX_ER | output | LED output for link or activity indication or receive error signal in MII mode synchronized with RX_CLK rising edge. |+| 47 | LED_0 | output | LED output for link or activity indication, part of VDDIO voltage domain. |+| 48 | VDDA1P8_2 | power_in | 1.8V analog power supply (±5%) for triple power mode, no connection required in dual power mode and must remain unconnected when unused. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | Interface |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `DP83869HMRGZT`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `dp83869hmrgzt-etched.step` / `dp83869hmrgzt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83869hmrgzt.step` / `dp83869hmrgzt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dp83869hm) (136 pp, sha256 `c9f251ea9e61fb66`, retrieved 2026-10-05, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dp83869hmrgzt-datasheet.pdf)
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"dp83869hmrgzt.glb",+ "model_3d_step": "dp83869hmrgzt-etched.step",+ "model_3d_step_plain": "dp83869hmrgzt.step",+ "lbr": "dp83869hmrgzt.lbr"+ },+ "distributor_links": {+ "lcsc": 2671580,+ "digikey": "296-53377-2-ND",+ "mouser": "595-DP83869HMRGZT"+ },+ "distributor_check": {+ "checked_at": "2026-10-05T18:55:32Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-53377-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DP83869HMRGZT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "TD_P_A",+ "type": "bidirectional",+ "description": "Differential transmit and receive signal for channel A, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor."+ },+ {+ "number": "2",+ "name": "TD_M_A",+ "type": "bidirectional",+ "description": "Differential transmit and receive signal for channel A, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor."+ },+ {+ "number": "3",+ "name": "VDDA2P5",+ "type": "power_in",+ "description": "2.5V analog power supply (±5%) requiring 1µF and 0.1µF capacitors to ground at each pin."+ },+ {+ "number": "4",+ "name": "TD_P_B",+ "type": "bidirectional",+ "description": "Differential transmit and receive signal for channel B, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor."+ },+ {+ "number": "5",+ "name": "TD_M_B",+ "type": "bidirectional",+ "description": "Differential transmit and receive signal for channel B, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor."+ },+ {+ "number": "6",+ "name": "VDD1P1",+ "type": "power_in",+ "description": "1.1V digital power supply (±10%) requiring 1µF and 0.1µF capacitors to ground at each pin."+ },+ {+ "number": "7",+ "name": "TD_P_C",+ "type": "bidirectional",+ "description": "Differential transmit and receive signal for channel C, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor."+ },+ {+ "number": "8",+ "name": "TD_M_C",+ "type": "bidirectional",+ "description": "Differential transmit and receive signal for channel C, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor."+ },+ {+ "number": "9",+ "name": "VDDA2P5",+ "type": "power_in",+ "description": "2.5V analog power supply (±5%) requiring 1µF and 0.1µF capacitors to ground at each pin."+ },+ {+ "number": "10",+ "name": "TD_P_D",+ "type": "bidirectional",+ "description": "Differential transmit and receive signal for channel D, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor."+ },+ {+ "number": "11",+ "name": "TD_M_D",+ "type": "bidirectional",+ "description": "Differential transmit and receive signal for channel D, provides LVDS signal AC-coupled to remote device with 0.1µF capacitor."+ },+ {+ "number": "12",+ "name": "RBIAS",+ "type": "passive",+ "description": "Bias resistor connection requiring external 11kΩ ±1% resistor connected to ground for impedance matching."+ },+ {+ "number": "13",+ "name": "VDDA1P8_1",+ "type": "power_in",+ "description": "1.8V analog power supply (±5%) for triple power mode, no connection required in dual power mode and must remain unconnected when unused."+ },+ {+ "number": "14",+ "name": "SON",+ "type": "output",+ "description": "Differential SGMII or fiber data output providing LVDS signal AC-coupled via 0.1µF capacitor from PHY to MAC or transceiver."+ },+ {+ "number": "15",+ "name": "SOP",+ "type": "output",+ "description": "Differential SGMII or fiber data output providing LVDS signal AC-coupled via 0.1µF capacitor from PHY to MAC or transceiver."+ },+ {+ "number": "16",+ "name": "SIP",+ "type": "input",+ "description": "Differential SGMII or fiber data input receiving LVDS signal AC-coupled via 0.1µF capacitor from MAC or transceiver to PHY."+ },+ {+ "number": "17",+ "name": "SIN",+ "type": "input",+ "description": "Differential SGMII or fiber data input receiving LVDS signal AC-coupled via 0.1µF capacitor from MAC or transceiver to PHY."+ },+ {+ "number": "18",+ "name": "VDDIO",+ "type": "power_in",+ "description": "I/O power supply selectable as 1.8V (±5%), 2.5V (±5%), or 3.3V (±5%) requiring 1µF and 0.1µF capacitors to ground."+ },+ {+ "number": "19",+ "name": "XO",+ "type": "output",+ "description": "Crystal oscillator output for 25MHz crystal secondary connection, must remain floating if external clock oscillator is used."+ },+ {+ "number": "20",+ "name": "XI",+ "type": "input",+ "description": "Crystal oscillator input for 25MHz reference clock from crystal or external CMOS oscillator."+ },+ {+ "number": "21",+ "name": "JTAG_CLK/TX_ER",+ "type": "input",+ "description": "JTAG test clock input per IEEE 1149.1 standard or MII transmit error signal in 100M mode with internal weak pull-up."+ },+ {+ "number": "22",+ "name": "JTAG_TDO/GPIO_1",+ "type": "output",+ "description": "JTAG test data output per IEEE 1149.1 standard or configurable GPIO output controlled by GPIO_MUX_CTRL register."+ },+ {+ "number": "23",+ "name": "JTAG_TMS",+ "type": "input",+ "description": "JTAG test mode select input per IEEE 1149.1 standard for TAP controller with internal weak pull-up."+ },+ {+ "number": "24",+ "name": "JTAG_TDI/SD",+ "type": "input",+ "description": "JTAG test data input per IEEE 1149.1 standard or active-low signal detect input for 1000Base-X and 100Base-FX fiber modes with weak pull-up."+ },+ {+ "number": "25",+ "name": "TX_D3",+ "type": "input",+ "description": "Transmit data bit 3 synchronized with transmit clock for RGMII and MII modes with internal weak pull-down."+ },+ {+ "number": "26",+ "name": "TX_D2",+ "type": "input",+ "description": "Transmit data bit 2 synchronized with transmit clock for RGMII and MII modes with internal weak pull-down."+ },+ {+ "number": "27",+ "name": "TX_D1",+ "type": "input",+ "description": "Transmit data bit 1 synchronized with transmit clock for RGMII and MII modes with internal weak pull-down."+ },+ {+ "number": "28",+ "name": "TX_D0",+ "type": "input",+ "description": "Transmit data bit 0 synchronized with transmit clock for RGMII and MII modes with internal weak pull-down."+ },+ {+ "number": "29",+ "name": "GTX_CLK/TX_CLK",+ "type": "bidirectional",+ "description": "RGMII transmit clock input at 125MHz or MII transmit clock output at 25MHz (100Mbps) or 2.5MHz (10Mbps) with mode-dependent direction."+ },+ {+ "number": "30",+ "name": "VDDIO",+ "type": "power_in",+ "description": "I/O power supply selectable as 1.8V (±5%), 2.5V (±5%), or 3.3V (±5%) requiring 1µF and 0.1µF capacitors to ground."+ },+ {+ "number": "31",+ "name": "VDD1P1",+ "type": "power_in",+ "description": "1.1V digital power supply (±10%) requiring 1µF and 0.1µF capacitors to ground at each pin."+ },+ {+ "number": "32",+ "name": "RX_CLK",+ "type": "output",+ "description": "Recovered receive clock output providing 125MHz for 1000Mbps RGMII mode and 25MHz for 100Mbps or 2.5MHz for 10Mbps modes."+ },+ {+ "number": "33",+ "name": "RX_D0",+ "type": "output",+ "description": "Receive data bit 0 from PHY to MAC synchronized with RX_CLK in RGMII and MII modes."+ },+ {+ "number": "34",+ "name": "RX_D1",+ "type": "output",+ "description": "Receive data bit 1 from PHY to MAC synchronized with RX_CLK in RGMII and MII modes."+ },+ {+ "number": "35",+ "name": "RX_D2",+ "type": "output",+ "description": "Receive data bit 2 from PHY to MAC synchronized with RX_CLK in RGMII and MII modes."+ },+ {+ "number": "36",+ "name": "RX_D3",+ "type": "output",+ "description": "Receive data bit 3 from PHY to MAC synchronized with RX_CLK in RGMII and MII modes."+ },+ {+ "number": "37",+ "name": "TX_CTRL/TX_EN",+ "type": "input",+ "description": "Transmit control in RGMII mode combining TX_EN and TX_ER on clock edges, or transmit enable in MII mode with internal weak pull-down."+ },+ {+ "number": "38",+ "name": "RX_CTRL/RX_DV",+ "type": "output",+ "description": "Receive control in RGMII mode combining RX_DV and RX_ER on clock edges, or receive data valid in MII mode."+ },+ {+ "number": "39",+ "name": "VDD1P1",+ "type": "power_in",+ "description": "1.1V digital power supply (±10%) requiring 1µF and 0.1µF capacitors to ground at each pin."+ },+ {+ "number": "40",+ "name": "CLK_OUT",+ "type": "output",+ "description": "Programmable clock output providing 25MHz default or configurable to 125/5MHz recovery clock per I/O configuration register."+ },+ {+ "number": "41",+ "name": "MDIO",+ "type": "bidirectional",+ "description": "Management data I/O for serial MDIO interface, open-drain requiring external 1.5kΩ pull-up resistor to VDDIO."+ },+ {+ "number": "42",+ "name": "MDC",+ "type": "input",+ "description": "Management data clock for MDIO synchronous interface operating up to 25MHz maximum frequency."+ },+ {+ "number": "43",+ "name": "RESET_N",+ "type": "input",+ "description": "Active-low reset input for device initialization requiring 100Ω series resistor and 47µF capacitor to ground."+ },+ {+ "number": "44",+ "name": "INT_N/PWDN_N",+ "type": "bidirectional",+ "description": "Configurable as active-low power down input or open-drain interrupt output per register control with internal pull-up."+ },+ {+ "number": "45",+ "name": "LED_2/GPIO_0",+ "type": "bidirectional",+ "description": "LED output or configurable GPIO output controlled by GPIO_MUX_CTRL register with polarity set by strap configuration."+ },+ {+ "number": "46",+ "name": "LED_1/RX_ER",+ "type": "output",+ "description": "LED output for link or activity indication or receive error signal in MII mode synchronized with RX_CLK rising edge."+ },+ {+ "number": "47",+ "name": "LED_0",+ "type": "output",+ "description": "LED output for link or activity indication, part of VDDIO voltage domain."+ },+ {+ "number": "48",+ "name": "VDDA1P8_2",+ "type": "power_in",+ "description": "1.8V analog power supply (±5%) for triple power mode, no connection required in dual power mode and must remain unconnected when unused."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Multiple power and ground pins with specific sequencing and decoupling requirements as detailed in s",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 79,+ "cost_usd": 0.6117,+ "at": "2026-10-05T18:55:15"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dp83869hm",+ "pages": 136,+ "sha256": "c9f251ea9e61fb66",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}