component
DP83867ERGZT
Public Made by Adomby adom
Texas Instruments Ethernet Transceivers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+86@@ -0,0 +1,86 @@+# DP83867ERGZT++**Texas Instruments** · Ethernet Transceivers · VQFN-48-EP(7x7)++DP83867ERGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | TD_P_A | bidirectional | Analog differential transmit/receive signal, channel A positive (MDI). |+| 2 | TD_M_A | bidirectional | Analog differential transmit/receive signal, channel A negative (MDI). |+| 3 | VDDA2P5 | power_in | 2.5V analog supply (±5%); each pin needs 1µF and 0.1µF capacitors to ground. |+| 4 | TD_P_B | bidirectional | Analog differential transmit/receive signal, channel B positive (MDI). |+| 5 | TD_M_B | bidirectional | Analog differential transmit/receive signal, channel B negative (MDI). |+| 6 | VDD1P0 | power_in | 1V analog supply (+15.5%, -5%); each pin needs 1µF and 0.1µF capacitors to ground. |+| 7 | TD_P_C | bidirectional | Analog differential transmit/receive signal, channel C positive (MDI). |+| 8 | TD_M_C | bidirectional | Analog differential transmit/receive signal, channel C negative (MDI). |+| 9 | VDDA2P5 | power_in | 2.5V analog supply (±5%); each pin needs 1µF and 0.1µF capacitors to ground. |+| 10 | TD_P_D | bidirectional | Analog differential transmit/receive signal, channel D positive (MDI). |+| 11 | TD_M_D | bidirectional | Analog differential transmit/receive signal, channel D negative (MDI). |+| 12 | RBIAS | passive | Bias resistor connection; connect an 11kΩ ±1% resistor from RBIAS to ground. |+| 13 | VDDA1P8 | power_in | 1.8V analog supply (±5%); no external supply required and must be left unconnected if unused, optional external 1.8V with 1µF and 0.1µF capacitors to save power. |+| 14 | XO | output | Crystal output, second terminal of the 25MHz crystal; leave floating when a clock oscillator is used. |+| 15 | XI | input | Crystal/oscillator input for 25MHz oscillator or crystal (50ppm). |+| 16 | MDC | input | Management data clock for MDIO serial management; maximum clock rate 25MHz, no minimum; internal pull-down. |+| 17 | MDIO | bidirectional | Bidirectional management data I/O; requires a pull-up resistor (1.5kΩ IEEE specified, 2.2kΩ acceptable). |+| 18 | CLK_OUT | output | Clock output pin. |+| 19 | VDDIO | power_in | I/O supply of 1.8V, 2.5V or 3.3V (±5%); each pin needs 1µF and 0.1µF capacitors to ground. |+| 20 | JTAG_CLK | input | IEEE 1149.1 JTAG test clock input, internal pull-up, maximum clock frequency 2.5MHz. |+| 21 | JTAG_TDO | output | IEEE 1149.1 JTAG test data output. |+| 22 | JTAG_TMS | input | IEEE 1149.1 JTAG test mode select with internal pull-up; hold high for 3 clock cycles to reset JTAG. |+| 23 | JTAG_TDI | input | IEEE 1149.1 JTAG test data input with internal pull-up. |+| 24 | VDD1P0 | power_in | 1V analog supply (+15.5%, -5%); each pin needs 1µF and 0.1µF capacitors to ground. |+| 25 | TX_D3 | input | RGMII transmit data bit 3 from MAC to PHY, synchronous to GTX_CLK; internal pull-down. |+| 26 | TX_D2 | input | RGMII transmit data bit 2 from MAC to PHY, synchronous to GTX_CLK; internal pull-down. |+| 27 | TX_D1/SGMII_SIP | input | RGMII transmit data bit 1, or SGMII differential data input positive (AC-coupled with 0.1µF); internal pull-down. |+| 28 | TX_D0/SGMII_SIN | input | RGMII transmit data bit 0, or SGMII differential data input negative (AC-coupled with 0.1µF); internal pull-down. |+| 29 | GTX_CLK | input | RGMII transmit clock supplied by the MAC, nominal 125MHz; internal pull-down. |+| 30 | VDDIO | power_in | I/O supply of 1.8V, 2.5V or 3.3V (±5%); each pin needs 1µF and 0.1µF capacitors to ground. |+| 31 | VDD1P0 | power_in | 1V analog supply (+15.5%, -5%); each pin needs 1µF and 0.1µF capacitors to ground. |+| 32 | RX_CLK | output | RGMII receive clock: 2.5MHz at 10Mbps, 25MHz at 100Mbps, 125MHz at 1000Mbps. |+| 33 | RX_D0/SGMII_COP | bidirectional | RGMII receive data bit 0, or SGMII 625MHz clock output positive; strap configuration pin (PHY_ADD1/PHY_ADD0), internal pull-down. |+| 34 | RX_D1/SGMII_CON | output | RGMII receive data bit 1, or SGMII 625MHz clock output negative; internal pull-down, needs the same dummy strap resistors as RX_D0. |+| 35 | RX_D2/SGMII_SOP | bidirectional | RGMII receive data bit 2, or SGMII data output positive; strap configuration pin (PHY_ADD3/PHY_ADD2), internal pull-down. |+| 36 | RX_D3/SGMII_SON | output | RGMII receive data bit 3, or SGMII data output negative; internal pull-down, needs the same dummy strap resistors as RX_D2. |+| 37 | TX_CTRL | input | RGMII transmit control combining transmit enable and error on both clock edges; internal pull-down. |+| 38 | RX_CTRL | bidirectional | RGMII receive control combining data valid and error (RXDV_ER) on both RX_CLK edges; strap pin for autonegotiation disable, internal pull-down. |+| 39 | GPIO_0 | bidirectional | Multi-function configurable GPIO per GPIO_MUX_CTRL register; strap pin for RGMII RX clock skew, internal pull-down. |+| 40 | GPIO_1 | bidirectional | Multi-function configurable GPIO per GPIO_MUX_CTRL register; strap pin for RGMII RX clock skew, internal pull-down. |+| 41 | VDDIO | power_in | I/O supply of 1.8V, 2.5V or 3.3V (±5%); each pin needs 1µF and 0.1µF capacitors to ground. |+| 42 | VDD1P0 | power_in | 1V analog supply (+15.5%, -5%); each pin needs 1µF and 0.1µF capacitors to ground. |+| 43 | RESET_N | input | Active-low reset with internal pull-up; must be held low for at least 1µs. |+| 44 | INT/PWDN | bidirectional | Active-low power-down input by default, or open-drain interrupt output (2.2kΩ pull-up to VDDIO recommended); internal pull-up. |+| 45 | LED_2 | bidirectional | LED output, default receive/transmit activity, configurable via LEDCR1[11:8]; strap pin for RGMII TX clock skew, internal pull-down. |+| 46 | LED_1 | bidirectional | LED output, default 1000BASE-T link established, configurable via LEDCR1[7:4]; strap pin for ANEG_SEL and RGMII TX clock skew, internal pull-down. |+| 47 | LED_0 | bidirectional | LED output, default link established, configurable via LEDCR1[3:0]; strap pin for mirror enable and SGMII enable, internal pull-down. |+| 48 | VDDA1P8 | power_in | 1.8V analog supply (±5%); no external supply required and must be left unconnected if unused, optional external 1.8V with 1µF and 0.1µF capacitors to save power. |+| 49 | GND | power_in | Die attach pad (exposed pad), ground. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | Interface |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `DP83867ERGZT`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `dp83867ergzt-etched.step` / `dp83867ergzt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83867ergzt.step` / `dp83867ergzt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dp83867is) (127 pp, sha256 `101dd83b84e239fd`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dp83867ergzt-datasheet.pdf)
page.jsonadded+447@@ -0,0 +1,447 @@+{+ "slug": "dp83867ergzt",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Ethernet Transceivers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "dp83867ergzt",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dp83867ergzt.kicad_sym",+ "dp83867ergzt.kicad_mod",+ "dp83867ergzt.glb",+ "dp83867ergzt.step",+ "dp83867ergzt.lbr",+ "docs/hero.png",+ "docs/dp83867ergzt-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "dp83867ergzt-hero.glb",+ "dp83867ergzt-hero.overlay.json"+ ],+ "component": {+ "mpn": "DP83867ERGZT",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-48-EP(7x7)",+ "pin_count": 49,+ "category": "Interface",+ "subcategory": "Ethernet Transceivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dp83867is",+ "parts": {+ "symbol": "dp83867ergzt.kicad_sym",+ "footprint": "dp83867ergzt.kicad_mod",+ "model_3d": "dp83867ergzt-hero.glb",+ "model_3d_plain": "dp83867ergzt.glb",+ "model_3d_step": "dp83867ergzt-etched.step",+ "model_3d_step_plain": "dp83867ergzt.step",+ "lbr": "dp83867ergzt.lbr"+ },+ "distributor_links": {+ "lcsc": "C2651886",+ "digikey": "296-43254-2-ND",+ "mouser": "595-DP83867ERGZT"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T20:04:18Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-43254-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DP83867ERGZT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "TD_P_A",+ "type": "bidirectional",+ "description": "Analog differential transmit/receive signal, channel A positive (MDI)."+ },+ {+ "number": "2",+ "name": "TD_M_A",+ "type": "bidirectional",+ "description": "Analog differential transmit/receive signal, channel A negative (MDI)."+ },+ {+ "number": "3",+ "name": "VDDA2P5",+ "type": "power_in",+ "description": "2.5V analog supply (±5%); each pin needs 1µF and 0.1µF capacitors to ground."+ },+ {+ "number": "4",+ "name": "TD_P_B",+ "type": "bidirectional",+ "description": "Analog differential transmit/receive signal, channel B positive (MDI)."+ },+ {+ "number": "5",+ "name": "TD_M_B",+ "type": "bidirectional",+ "description": "Analog differential transmit/receive signal, channel B negative (MDI)."+ },+ {+ "number": "6",+ "name": "VDD1P0",+ "type": "power_in",+ "description": "1V analog supply (+15.5%, -5%); each pin needs 1µF and 0.1µF capacitors to ground."+ },+ {+ "number": "7",+ "name": "TD_P_C",+ "type": "bidirectional",+ "description": "Analog differential transmit/receive signal, channel C positive (MDI)."+ },+ {+ "number": "8",+ "name": "TD_M_C",+ "type": "bidirectional",+ "description": "Analog differential transmit/receive signal, channel C negative (MDI)."+ },+ {+ "number": "9",+ "name": "VDDA2P5",+ "type": "power_in",+ "description": "2.5V analog supply (±5%); each pin needs 1µF and 0.1µF capacitors to ground."+ },+ {+ "number": "10",+ "name": "TD_P_D",+ "type": "bidirectional",+ "description": "Analog differential transmit/receive signal, channel D positive (MDI)."+ },+ {+ "number": "11",+ "name": "TD_M_D",+ "type": "bidirectional",+ "description": "Analog differential transmit/receive signal, channel D negative (MDI)."+ },+ {+ "number": "12",+ "name": "RBIAS",+ "type": "passive",+ "description": "Bias resistor connection; connect an 11kΩ ±1% resistor from RBIAS to ground."+ },+ {+ "number": "13",+ "name": "VDDA1P8",+ "type": "power_in",+ "description": "1.8V analog supply (±5%); no external supply required and must be left unconnected if unused, optional external 1.8V with 1µF and 0.1µF capacitors to save power."+ },+ {+ "number": "14",+ "name": "XO",+ "type": "output",+ "description": "Crystal output, second terminal of the 25MHz crystal; leave floating when a clock oscillator is used."+ },+ {+ "number": "15",+ "name": "XI",+ "type": "input",+ "description": "Crystal/oscillator input for 25MHz oscillator or crystal (50ppm)."+ },+ {+ "number": "16",+ "name": "MDC",+ "type": "input",+ "description": "Management data clock for MDIO serial management; maximum clock rate 25MHz, no minimum; internal pull-down."+ },+ {+ "number": "17",+ "name": "MDIO",+ "type": "bidirectional",+ "description": "Bidirectional management data I/O; requires a pull-up resistor (1.5kΩ IEEE specified, 2.2kΩ acceptable)."+ },+ {+ "number": "18",+ "name": "CLK_OUT",+ "type": "output",+ "description": "Clock output pin."+ },+ {+ "number": "19",+ "name": "VDDIO",+ "type": "power_in",+ "description": "I/O supply of 1.8V, 2.5V or 3.3V (±5%); each pin needs 1µF and 0.1µF capacitors to ground."+ },+ {+ "number": "20",+ "name": "JTAG_CLK",+ "type": "input",+ "description": "IEEE 1149.1 JTAG test clock input, internal pull-up, maximum clock frequency 2.5MHz."+ },+ {+ "number": "21",+ "name": "JTAG_TDO",+ "type": "output",+ "description": "IEEE 1149.1 JTAG test data output."+ },+ {+ "number": "22",+ "name": "JTAG_TMS",+ "type": "input",+ "description": "IEEE 1149.1 JTAG test mode select with internal pull-up; hold high for 3 clock cycles to reset JTAG."+ },+ {+ "number": "23",+ "name": "JTAG_TDI",+ "type": "input",+ "description": "IEEE 1149.1 JTAG test data input with internal pull-up."+ },+ {+ "number": "24",+ "name": "VDD1P0",+ "type": "power_in",+ "description": "1V analog supply (+15.5%, -5%); each pin needs 1µF and 0.1µF capacitors to ground."+ },+ {+ "number": "25",+ "name": "TX_D3",+ "type": "input",+ "description": "RGMII transmit data bit 3 from MAC to PHY, synchronous to GTX_CLK; internal pull-down."+ },+ {+ "number": "26",+ "name": "TX_D2",+ "type": "input",+ "description": "RGMII transmit data bit 2 from MAC to PHY, synchronous to GTX_CLK; internal pull-down."+ },+ {+ "number": "27",+ "name": "TX_D1/SGMII_SIP",+ "type": "input",+ "description": "RGMII transmit data bit 1, or SGMII differential data input positive (AC-coupled with 0.1µF); internal pull-down."+ },+ {+ "number": "28",+ "name": "TX_D0/SGMII_SIN",+ "type": "input",+ "description": "RGMII transmit data bit 0, or SGMII differential data input negative (AC-coupled with 0.1µF); internal pull-down."+ },+ {+ "number": "29",+ "name": "GTX_CLK",+ "type": "input",+ "description": "RGMII transmit clock supplied by the MAC, nominal 125MHz; internal pull-down."+ },+ {+ "number": "30",+ "name": "VDDIO",+ "type": "power_in",+ "description": "I/O supply of 1.8V, 2.5V or 3.3V (±5%); each pin needs 1µF and 0.1µF capacitors to ground."+ },+ {+ "number": "31",+ "name": "VDD1P0",+ "type": "power_in",+ "description": "1V analog supply (+15.5%, -5%); each pin needs 1µF and 0.1µF capacitors to ground."+ },+ {+ "number": "32",+ "name": "RX_CLK",+ "type": "output",+ "description": "RGMII receive clock: 2.5MHz at 10Mbps, 25MHz at 100Mbps, 125MHz at 1000Mbps."+ },+ {+ "number": "33",+ "name": "RX_D0/SGMII_COP",+ "type": "bidirectional",+ "description": "RGMII receive data bit 0, or SGMII 625MHz clock output positive; strap configuration pin (PHY_ADD1/PHY_ADD0), internal pull-down."+ },+ {+ "number": "34",+ "name": "RX_D1/SGMII_CON",+ "type": "output",+ "description": "RGMII receive data bit 1, or SGMII 625MHz clock output negative; internal pull-down, needs the same dummy strap resistors as RX_D0."+ },+ {+ "number": "35",+ "name": "RX_D2/SGMII_SOP",+ "type": "bidirectional",+ "description": "RGMII receive data bit 2, or SGMII data output positive; strap configuration pin (PHY_ADD3/PHY_ADD2), internal pull-down."+ },+ {+ "number": "36",+ "name": "RX_D3/SGMII_SON",+ "type": "output",+ "description": "RGMII receive data bit 3, or SGMII data output negative; internal pull-down, needs the same dummy strap resistors as RX_D2."+ },+ {+ "number": "37",+ "name": "TX_CTRL",+ "type": "input",+ "description": "RGMII transmit control combining transmit enable and error on both clock edges; internal pull-down."+ },+ {+ "number": "38",+ "name": "RX_CTRL",+ "type": "bidirectional",+ "description": "RGMII receive control combining data valid and error (RXDV_ER) on both RX_CLK edges; strap pin for autonegotiation disable, internal pull-down."+ },+ {+ "number": "39",+ "name": "GPIO_0",+ "type": "bidirectional",+ "description": "Multi-function configurable GPIO per GPIO_MUX_CTRL register; strap pin for RGMII RX clock skew, internal pull-down."+ },+ {+ "number": "40",+ "name": "GPIO_1",+ "type": "bidirectional",+ "description": "Multi-function configurable GPIO per GPIO_MUX_CTRL register; strap pin for RGMII RX clock skew, internal pull-down."+ },+ {+ "number": "41",+ "name": "VDDIO",+ "type": "power_in",+ "description": "I/O supply of 1.8V, 2.5V or 3.3V (±5%); each pin needs 1µF and 0.1µF capacitors to ground."+ },+ {+ "number": "42",+ "name": "VDD1P0",+ "type": "power_in",+ "description": "1V analog supply (+15.5%, -5%); each pin needs 1µF and 0.1µF capacitors to ground."+ },+ {+ "number": "43",+ "name": "RESET_N",+ "type": "input",+ "description": "Active-low reset with internal pull-up; must be held low for at least 1µs."+ },+ {+ "number": "44",+ "name": "INT/PWDN",+ "type": "bidirectional",+ "description": "Active-low power-down input by default, or open-drain interrupt output (2.2kΩ pull-up to VDDIO recommended); internal pull-up."+ },+ {+ "number": "45",+ "name": "LED_2",+ "type": "bidirectional",+ "description": "LED output, default receive/transmit activity, configurable via LEDCR1[11:8]; strap pin for RGMII TX clock skew, internal pull-down."+ },+ {+ "number": "46",+ "name": "LED_1",+ "type": "bidirectional",+ "description": "LED output, default 1000BASE-T link established, configurable via LEDCR1[7:4]; strap pin for ANEG_SEL and RGMII TX clock skew, internal pull-down."+ },+ {+ "number": "47",+ "name": "LED_0",+ "type": "bidirectional",+ "description": "LED output, default link established, configurable via LEDCR1[3:0]; strap pin for mirror enable and SGMII enable, internal pull-down."+ },+ {+ "number": "48",+ "name": "VDDA1P8",+ "type": "power_in",+ "description": "1.8V analog supply (±5%); no external supply required and must be left unconnected if unused, optional external 1.8V with 1µF and 0.1µF capacitors to save power."+ },+ {+ "number": "49",+ "name": "GND",+ "type": "power_in",+ "description": "Die attach pad (exposed pad), ground."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed die-attach pad (GND, labelled DAP) is listed in the datasheet as a ground connection wit; The datasheet is a Chinese translation of the TI document; pin descriptions were rendered in English; Multiplexed pins 27, 28, 33, 34, 35 and 36 serve both RGMII and SGMII. The name field lists both fun",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 63,+ "cost_usd": 0.3447,+ "at": "2026-10-08T20:03:46"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dp83867is",+ "pages": 127,+ "sha256": "101dd83b84e239fd",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dp83867ergzt.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dp83867ergzt-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "ac830dd324b2829e939b12940f49929e89e834932e7c82414fb05e43843218cc",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}