dg409ledy-t1-ge3

@@ -0,0 +1,59 @@+# DG409LEDY-T1-GE3++**Vishay** · Analog Switches, Multiplexers · SOIC-16++DG409LEDY-T1-GE3 from Vishay, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A0 | input | TTL/CMOS-compatible binary address input, bit 0. Together with A1 selects which of the four differential channels (S1a/S1b through S4a/S4b) is routed to the Da/Db common drains. VINH = 2.4 V (min), VINL = 0.8 V (max) at V+ = 12 V. |+| 2 | EN | input | TTL/CMOS-compatible active-high enable input. EN = 1 enables the addressed switch; EN = 0 forces all channels off, allowing devices to be stacked. Input current ±1 µA max. |+| 3 | V- | power_in | Negative analog supply rail. Ground for single-supply operation (3 V to 16 V), or negative rail for dual-supply operation (−3 V to −8 V). V+ to V- must not exceed 18 V. |+| 4 | S1a | passive | Analog source input of bank-a channel 1. Bidirectional analog switch terminal; connects to Da when A1=0, A0=0, EN=1. Signal range 0 to V+ (single supply) or V- to V+ (dual supply). RDS(on) ≈ 17 Ω typ. |+| 5 | S2a | passive | Analog source input of bank-a channel 2. Routed to Da when A1=0, A0=1, EN=1. Same analog range and on-resistance as other S pins. |+| 6 | S3a | passive | Analog source input of bank-a channel 3. Routed to Da when A1=1, A0=0, EN=1. |+| 7 | S4a | passive | Analog source input of bank-a channel 4. Routed to Da when A1=1, A0=1, EN=1. |+| 8 | Da | passive | Common analog drain of bank a. Bidirectional; connects to one of S1a..S4a based on the (A1, A0) address when EN is high. Drain-on capacitance ≈ 23.5 pF typ. |+| 9 | Db | passive | Common analog drain of bank b. Bidirectional; connects to one of S1b..S4b based on the same (A1, A0) address when EN is high. Paired with Da to form a differential common output. |+| 10 | S4b | passive | Analog source input of bank-b channel 4. Routed to Db when A1=1, A0=1, EN=1. Paired with S4a to form differential channel 4. |+| 11 | S3b | passive | Analog source input of bank-b channel 3. Routed to Db when A1=1, A0=0, EN=1. Paired with S3a. |+| 12 | S2b | passive | Analog source input of bank-b channel 2. Routed to Db when A1=0, A0=1, EN=1. Paired with S2a. |+| 13 | S1b | passive | Analog source input of bank-b channel 1. Routed to Db when A1=0, A0=0, EN=1. Paired with S1a. |+| 14 | V+ | power_in | Positive analog supply rail. 3 V to 16 V for single-supply operation, or +3 V to +8 V for dual-supply operation. Powers the internal voltage regulator and logic. Quiescent current ≈ 3.5 µA (typ), 6 µA max. |+| 15 | GND | power_in | Digital ground reference for the logic inputs (A0, A1, EN). GND to V- must be ≥ -18 V (i.e., V- may be up to 18 V below GND). |+| 16 | A1 | input | TTL/CMOS-compatible binary address input, bit 1. Together with A0 selects which of the four differential channels is on when EN = 1. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Vishay |+| Package | SOIC-16 |+| Category | Interface |+| Pins | 16 |++## Ordering variants++- `DG409LEDY-T1-GE3DG409LEDY-GE3`+- `DG409LEDY-T1-GE3`+- `DG409LEDY-T1-GE3DG409LEDQ-GE3`+- `DG409LEDY-T1-GE3DG409LEDQ-T1-GE3`+- `DG409LEDY-T1-GE3DG409LEDN-T1-GE4`++## CAD (KiCad official)++- Symbol: `DG409LEDY-T1-GE3`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Vishay datasheet](docs/dg409ledy-t1-ge3-datasheet.pdf) (None pp, sha256 `25c17230a1edebf9`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dg409ledy-t1-ge3-datasheet.pdf)

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