component
DAC8814ICDBR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), SSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
Publish 0.1.1
7 files changed
+851−839
README.md+55−50@@ -8,34 +8,34 @@ DAC8814ICDBR from Texas Instruments, in a SSOP-28. Pinout and pin descriptions e | Pin | Name | Type | Function | |---|---|---|---|-| 1 | AGNDA | power_in | DAC A analog ground. |-| 2 | IOUTA | output | DAC A current output. |-| 3 | VREFA | input | DAC A reference voltage input that establishes the DAC A full-scale output and can be tied to VDD. |-| 4 | RFBA | passive | DAC A feedback resistor terminal that sets the output voltage by connecting to the external amplifier output. |-| 5 | MSB | input | MSB bit set during a reset pulse (RS) or at system power-on, tied to ground or VDD, selecting zero-scale (0) or half-scale 8000h (1). |-| 6 | RS | input | Active-low reset that sets the input and DAC registers to all zeros or half-scale code (8000h) according to the MSB pin voltage. |-| 7 | VDD | power_in | Positive power-supply input with a specified operating range of +2.7 V to +5.5 V. |-| 8 | CS | input | Active-low chip select that disables shift register loading when high and transfers shift register data to the input register when CS goes high. |-| 9 | CLK | input | Clock input where the positive edge clocks data into the shift register. |-| 10 | SDI | input | Serial data input that loads directly into the shift register. |-| 11 | RFBB | passive | DAC B feedback resistor terminal that sets the output voltage by connecting to the external amplifier output. |-| 12 | VREFB | input | DAC B reference voltage input that establishes the DAC B full-scale output and can be tied to VDD. |-| 13 | IOUTB | output | DAC B current output. |-| 14 | AGNDB | power_in | DAC B analog ground. |-| 15 | AGNDC | power_in | DAC C analog ground. |-| 16 | IOUTC | output | DAC C current output. |-| 17 | VREFC | input | DAC C reference voltage input that establishes the DAC C full-scale output and can be tied to VDD. |-| 18 | RFBC | passive | DAC C feedback resistor terminal that sets the output voltage by connecting to the external amplifier output. |+| 1 | AGNDA | power_in | DAC A analog ground; the datasheet recommends connecting all AGNDX pins directly to an analog ground plane at the unit. |+| 2 | IOUTA | output | DAC A current output, whose full-scale value is set by the reference voltage on VREFA (2 mA full-scale current). |+| 3 | VREFA | input | DAC A reference voltage input that establishes the full-scale output voltage; it can be tied to VDD. |+| 4 | RFBA | input | DAC A feedback resistor connection that establishes the output voltage when connected to the external amplifier output. |+| 5 | MSB | input | Sets the code loaded by a reset pulse (RS) or at power-on: tied to ground loads zero code, tied to VDD loads half-scale (8000h). |+| 6 | RS | input | Active-low reset that forces the input and DAC registers to zero code or half-scale code as selected by MSB; may be tied high if not used. |+| 7 | VDD | power_in | Positive power supply input with a specified operating range of +2.7 V to +5.5 V. |+| 8 | CS | input | Active-low chip select that disables shift register loading when high and transfers shift register data to the input register on its rising edge. |+| 9 | CLK | input | Clock input; data is clocked into the shift register on the positive edge (SPI-compatible interface rated to 50 MHz). |+| 10 | SDI | input | Serial data input; data loads directly into the shift register. |+| 11 | RFBB | input | DAC B feedback resistor connection that establishes the output voltage when connected to the external amplifier output. |+| 12 | VREFB | input | DAC B reference voltage input that establishes the full-scale output voltage; it can be tied to VDD. |+| 13 | IOUTB | output | DAC B current output, whose full-scale value is set by the reference voltage on VREFB. |+| 14 | AGNDB | power_in | DAC B analog ground; the datasheet recommends connecting all AGNDX pins directly to an analog ground plane at the unit. |+| 15 | AGNDC | power_in | DAC C analog ground; the datasheet recommends connecting all AGNDX pins directly to an analog ground plane at the unit. |+| 16 | IOUTC | output | DAC C current output, whose full-scale value is set by the reference voltage on VREFC. |+| 17 | VREFC | input | DAC C reference voltage input that establishes the full-scale output voltage; it can be tied to VDD. |+| 18 | RFBC | input | DAC C feedback resistor connection that establishes the output voltage when connected to the external amplifier output. | | 19 | NC | unconnected | Not connected internally; leave floating. |-| 20 | SDO | output | Serial data output where data appears 19 clock pulses after input at the SDI pin, allowing daisy-chaining. |-| 21 | LDAC | input | Asynchronous, level-sensitive active-low load strobe that transfers all input register data to the DAC registers. |-| 22 | AGNDF | power_in | High current analog force ground. |-| 23 | VSS | power_in | No internal connection. |+| 20 | SDO | output | Serial data output for daisy-chaining; data appears 19 clock pulses after the input at SDI. |+| 21 | LDAC | input | Level-sensitive active-low asynchronous strobe that transfers all input register data to the DAC registers. |+| 22 | AGNDF | power_in | High-current analog force ground. |+| 23 | VSS | power_in | Listed as having no internal connection in the pin description table. | | 24 | DGND | power_in | Digital ground. |-| 25 | RFBD | passive | DAC D feedback resistor terminal that sets the output voltage by connecting to the external amplifier output. |-| 26 | VREFD | input | DAC D reference voltage input that establishes the DAC D full-scale output and can be tied to VDD. |-| 27 | IOUTD | output | DAC D current output. |-| 28 | AGNDD | power_in | DAC D analog ground. |+| 25 | RFBD | input | DAC D feedback resistor connection that establishes the output voltage when connected to the external amplifier output. |+| 26 | VREFD | input | DAC D reference voltage input that establishes the full-scale output voltage; it can be tied to VDD. |+| 27 | IOUTD | output | DAC D current output, whose full-scale value is set by the reference voltage on VREFD. |+| 28 | AGNDD | power_in | DAC D analog ground; the datasheet recommends connecting all AGNDX pins directly to an analog ground plane at the unit. | ## Key specifications @@ -52,15 +52,13 @@ Limits as printed in the datasheet (page.json `metadata.characteristics` carries | Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page | |---|---|---|---|---|---|---|---|-| Relative accuracy DAC8814C | INL | -1 | | 1 | LSB | DAC8814C | 3 |-| Differential nonlinearity DAC8814C | DNL | -1 | | 1 | LSB | DAC8814C | 3 |+| Relative accuracy | INL | -1 | | 1 | LSB | DAC8814C grade | 3 |+| Differential nonlinearity | DNL | -1 | | 1 | LSB | DAC8814C grade | 3 | | Output leakage current | IOUTX | | | 10 | nA | Data = 0000h, TA = 25°C | 3 |-| Output leakage current hot | IOUTX | | | 20 | nA | Data = 0000h, TA = TA max | 3 |-| Full-scale gain error | GFSE | | 0.75 | 3 | mV | Data = FFFFh (typ ±0.75, max ±3) | 3 |-| Full-scale tempco | TCVFS | | 1 | | ppm/°C | | 3 |-| Feedback resistor | RFBX | | 5 | | kΩ | VDD = 5 V | 3 |+| Output leakage current | IOUTX | | | 20 | nA | Data = 0000h, TA = TA max | 3 |+| Full-scale gain error | GFSE | -3 | 0.75 | 3 | mV | Data = FFFFh | 3 | | VREFX range | VREFX | -15 | | 15 | V | | 3 |-| Reference input resistance | RREFX | 4 | 5 | 6 | kΩ | | 3 |+| Input resistance | RREFX | 4 | 5 | 6 | kΩ | | 3 | | Input resistance match | RREFX | | | 1 | % | Channel-to-channel | 3 | | Output current | IOUTX | 1.6 | 2.5 | | mA | Data = FFFFh | 3 | | Input low voltage | VIL | | | 0.6 | V | VDD = +2.7 V | 3 |@@ -73,36 +71,43 @@ Limits as printed in the datasheet (page.json `metadata.characteristics` carries | Clock input frequency | fCLK | | | 50 | MHz | | 3 | | Clock width high | tCH | 10 | | | ns | | 3 | | Clock width low | tCL | 10 | | | ns | | 3 |-| CS to Clock setup | tCSS | 0 | | | ns | | 3 |+| CS to clock setup | tCSS | 0 | | | ns | | 3 | | Clock to CS hold | tCSH | 10 | | | ns | | 3 |-| Clock to SDO prop delay | tPD | 2 | | 20 | ns | | 3 |+| Clock to SDO propagation delay | tPD | 2 | | 20 | ns | | 3 | | Load DAC pulsewidth | tLDAC | 25 | | | ns | | 3 | | Data setup | tDS | 5 | | | ns | | 3 | | Data hold | tDH | 10 | | | ns | | 3 | | Load setup | tLDS | 5 | | | ns | | 3 | | Load hold | tLDH | 10 | | | ns | | 3 |-| Power supply range | VDD RANGE | 2.7 | | 5.5 | V | | 4 |+| Power supply range | VDD | 2.7 | | 5.5 | V | VDD RANGE | 4 | | Positive supply current | IDD | | 2 | 5 | µA | Logic inputs = 0 V, VDD = +4.5 V to +5.5 V | 4 | | Positive supply current | IDD | | 1 | 2.5 | µA | Logic inputs = 0 V, VDD = +2.7 V to +3.6 V | 4 |-| Power dissipation | PDISS | | | 0.0275 | mW | Logic inputs = 0 V | 4 |-| Power supply sensitivity | PSS | | 0.006 | | % | ∆VDD = ±5% | 4 | | VDD to GND | VDD | -0.3 | | 8 | V | | 2 | | VREF to GND | VREF | -18 | | 18 | V | | 2 | | Logic inputs and output to GND | | -0.3 | | 8 | V | | 2 |-| AGNDX to DGND | | -0.3 | | 0.3 | V | | 2 |+| V(IOUT) to GND | V(IOUT) | -0.3 | | | V | Upper limit printed as VDD + 0.3 V | 2 |+| AGNDX to DGND | AGNDX | -0.3 | | 0.3 | V | | 2 | | Input current to any pin except supplies | | -50 | | 50 | mA | | 2 | | Maximum junction temperature | TJmax | | | 150 | °C | | 2 | | Storage temperature range | | -65 | | 150 | °C | | 2 |-| Operating temperature range | | -40 | | 85 | °C | | 2 |-| ESD rating, HBM | | | | 3000 | V | | 2 |-| ESD rating, CDM | | | | 500 | V | | 2 |-| Thermal resistance | θJA | | 100 | | °C/W | 28-Lead shrink surface-mount (RS-28) | 2 |-| Reference input capacitance | CREFX | | 5 | | pF | | 3 |+| Operating temperature range, Model A | | -40 | | 85 | °C | Model A | 2 |+| ESD rating, HBM | | | | 3000 | V | ESD rating, HBM | 2 |+| ESD rating, CDM | | | | 500 | V | ESD rating, CDM | 2 |+| Thermal resistance, junction-to-ambient | θJA | | 100 | | °C/W | 28-Lead shrink surface-mount (RS-28) | 2 |+| Full-scale tempco | TCVFS | | 1 | | ppm/°C | | 3 |+| Feedback resistor | RFBX | | 5 | | kΩ | VDD = 5 V | 3 |+| Input capacitance | CREFX | | 5 | | pF | | 3 | | Output capacitance | COUTX | | 50 | | pF | Code-dependent | 3 |-| Logic input capacitance | CIL | | 10 | | pF | | 3 |-| Settling time | ts | | 0.3 | | µs | To ±0.1% of full-scale, Data = 0000h to FFFFh to 0000h | 4 |-| Settling time | ts | | 0.5 | | µs | To ±0.0015% of full-scale, Data = 0000h to FFFFh to 0000h | 4 |-| Reference multiplying BW | BW | | 10 | | MHz | -3 dB VREFX = 100 mVRMS, Data = FFFFh, CFB = 3 pF | 4 |+| Input capacitance | CIL | | 10 | | pF | | 3 |+| Power dissipation | PDISS | | 0.0275 | | mW | Logic inputs = 0 V | 4 |+| Power supply sensitivity | PSS | | 0.006 | | % | ΔVDD = ±5% | 4 |+| Output voltage settling time | ts | | 0.3 | | µs | To ±0.1% of full-scale, Data = 0000h to FFFFh to 0000h | 4 |+| Output voltage settling time | ts | | 0.5 | | µs | To ±0.0015% of full-scale, Data = 0000h to FFFFh to 0000h | 4 |+| Reference multiplying bandwidth | BW | | 10 | | MHz | BW -3 dB, VREFX = 100 mVRMS, Data = FFFFh, CFB = 3 pF | 4 |+| DAC glitch impulse | Q | | 5 | | nV-s | VREFX = 10 V, Data = 7FFFh to 8000h to 7FFFh | 4 |+| Feedthrough error | VOUTX/VREFX | | -70 | | dB | Data = 0000h, VREFX = 100 mVRMS, f = 100 kHz | 4 |+| Crosstalk error | VOUTA/VREFB | | -100 | | dB | Data = 0000h, VREFB = 100 mVRMS, adjacent channel, f = 100 kHz | 4 |+| Digital feedthrough | Q | | 1 | | nV-s | CS = 1 and fCLK = 1 MHz | 4 | | Total harmonic distortion | THD | | -105 | | dB | VREF = 5 VPP, Data = FFFFh, f = 1 kHz | 4 | | Output spot noise voltage | en | | 12 | | nV/√Hz | f = 1 kHz, BW = 1 Hz | 4 | @@ -117,8 +122,8 @@ Limits as printed in the datasheet (page.json `metadata.characteristics` carries Data extracted from the manufacturer datasheet, not a distributor listing: -- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/dac8814icdbr.pdf) (30 pp, sha256 `3c2f9c3850224afa`, retrieved 2026-11-12, tier: manufacturer)-- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/dac8814.pdf) (30 pp, sha256 `ac0123b387c7c750`, retrieved 2026-11-12, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - **CAD:** KiCad official libraries (CC-BY-SA 4.0). [Datasheet PDF](docs/dac8814icdbr-datasheet.pdf)
dac8814icdbr-hero.overlay.json+703−698@@ -1,700 +1,705 @@ {- "spec": "adom-hero 1.4",- "mpn": "DAC8814ICDBR",- "kind": "component + footprint reference art",- "board_use": false,- "plane_z_mm": -0.02,- "units": "metre",- "upAxis": "Z",- "layers": {- "pad_outlines": {- "material": "Footprint pads - teal dashed outlines - 50 percent opacity",- "rgba": [- 0.0,- 0.902,- 0.863,- 0.5- ],- "pads": 28,- "span_mm": 8.9,- "dash_mm": 0.2225,- "gap_mm": 0.1335,- "pad_stroke_mm": 0.0534- },- "silkscreen": {- "material": "Silkscreen reference lines - 30 percent opacity",- "rgba": [- 0.92,- 0.96,- 1.0,- 0.3- ],- "footprint_items": 7,- "pin1": {- "source": "footprint silkscreen",- "pad": "1"- }- },- "signal_names": {- "material": "Signal names - 50 percent opacity",- "rgba": [- 0.92,- 0.96,- 1.0,- 0.5- ],- "font": "DejaVu Sans Mono",- "labels": 28,- "sides": "top + mirrored underside (single-sided)",- "fallback_to_pad_number": 0- }- },- "align": {- "ok": true,- "centre_offset_mm": 0.0,- "tolerance_mm": 0.712,- "orientation_flipped": false,- "contacts_bbox_mm": [- -3.9,- 3.9,- -4.906,- 4.906- ],- "pads_bbox_mm": [- -4.45,- 4.45,- -4.425,- 4.425- ],- "seating_z_mm": 0.0- },- "sources": {- "glb": "dac8814icdbr-etched.glb",- "glb_sha256": "ea760c3bfab19ca99fa8234270cf956890638aaa8933212b16e2b647b97f30b9",- "footprint": "dac8814icdbr.kicad_mod",- "footprint_sha256": "bbb0d0449b996c0ad096ca837fee38110e319360b863de5c7df6a964f6140d98",- "pins": "page.json component.pins",- "pins_sha256": "4d3354190d6c8b2cb69629bc7a9fe4b3974c292b4bfbb38661e0c1bb368c86e9"- },- "generator": "adom-wiki 1.8.22 (component_hero)",- "labels": [- {- "pad": "1",- "text": "AGNDA",- "x": -4.55,- "y": -4.225,- "align": "right",- "vertical": false,- "h": 0.325- },- {- "pad": "2",- "text": "IOUTA",- "x": -4.55,- "y": -3.575,- "align": "right",- "vertical": false,- "h": 0.325- },- {- "pad": "3",- "text": "VREFA",- "x": -4.55,- "y": -2.925,- "align": "right",- "vertical": false,- "h": 0.325- },- {- "pad": "4",- "text": "RFBA",- "x": -4.55,- "y": -2.275,- "align": "right",- "vertical": false,- "h": 0.325- },- {- "pad": "5",- "text": "MSB",- "x": -4.55,- "y": -1.625,- "align": "right",- "vertical": false,- "h": 0.325- },- {- "pad": "6",- "text": "RS",- "x": -4.55,- "y": -0.975,- "align": "right",- "vertical": false,- "h": 0.325- },- {- "pad": "7",- "text": "VDD",- "x": -4.55,- "y": -0.325,- "align": "right",- "vertical": false,- "h": 0.325- },- {- "pad": "8",- "text": "CS",- "x": -4.55,- "y": 0.325,- "align": "right",- "vertical": false,- "h": 0.325- },- {- "pad": "9",- "text": "CLK",- "x": -4.55,- "y": 0.975,- "align": "right",- "vertical": false,- "h": 0.325- },- {- "pad": "10",- "text": "SDI",- "x": -4.55,- "y": 1.625,- "align": "right",- "vertical": false,- "h": 0.325- },- {- "pad": "11",- "text": "RFBB",- "x": -4.55,- "y": 2.275,- "align": "right",- "vertical": false,- "h": 0.325- },- {- "pad": "12",- "text": "VREFB",- "x": -4.55,- "y": 2.925,- "align": "right",- "vertical": false,- "h": 0.325- },- {- "pad": "13",- "text": "IOUTB",- "x": -4.55,- "y": 3.575,- "align": "right",- "vertical": false,- "h": 0.325- },- {- "pad": "14",- "text": "AGNDB",- "x": -4.55,- "y": 4.225,- "align": "right",- "vertical": false,- "h": 0.325- },- {- "pad": "15",- "text": "AGNDC",- "x": 4.55,- "y": 4.225,- "align": "left",- "vertical": false,- "h": 0.325- },- {- "pad": "16",- "text": "IOUTC",- "x": 4.55,- "y": 3.575,- "align": "left",- "vertical": false,- "h": 0.325- },- {- "pad": "17",- "text": "VREFC",- "x": 4.55,- "y": 2.925,- "align": "left",- "vertical": false,- "h": 0.325- },- {- "pad": "18",- "text": "RFBC",- "x": 4.55,- "y": 2.275,- "align": "left",- "vertical": false,- "h": 0.325- },- {- "pad": "19",- "text": "NC",- "x": 4.55,- "y": 1.625,- "align": "left",- "vertical": false,- "h": 0.325- },- {- "pad": "20",- "text": "SDO",- "x": 4.55,- "y": 0.975,- "align": "left",- "vertical": false,- "h": 0.325- },- {- "pad": "21",- "text": "LDAC",- "x": 4.55,- "y": 0.325,- "align": "left",- "vertical": false,- "h": 0.325- },- {- "pad": "22",- "text": "AGNDF",- "x": 4.55,- "y": -0.325,- "align": "left",- "vertical": false,- "h": 0.325- },- {- "pad": "23",- "text": "VSS",- "x": 4.55,- "y": -0.975,- "align": "left",- "vertical": false,- "h": 0.325- },- {- "pad": "24",- "text": "DGND",- "x": 4.55,- "y": -1.625,- "align": "left",- "vertical": false,- "h": 0.325- },- {- "pad": "25",- "text": "RFBD",- "x": 4.55,- "y": -2.275,- "align": "left",- "vertical": false,- "h": 0.325- },- {- "pad": "26",- "text": "VREFD",- "x": 4.55,- "y": -2.925,- "align": "left",- "vertical": false,- "h": 0.325- },- {- "pad": "27",- "text": "IOUTD",- "x": 4.55,- "y": -3.575,- "align": "left",- "vertical": false,- "h": 0.325- },- {- "pad": "28",- "text": "AGNDD",- "x": 4.55,- "y": -4.225,- "align": "left",- "vertical": false,- "h": 0.325- }+ "spec": "adom-hero 1.4",+ "mpn": "DAC8814ICDBR",+ "kind": "component + footprint reference art",+ "board_use": false,+ "plane_z_mm": -0.02,+ "units": "metre",+ "upAxis": "Z",+ "layers": {+ "pad_outlines": {+ "material": "Footprint pads - teal dashed outlines - 50 percent opacity",+ "rgba": [+ 0.0,+ 0.902,+ 0.863,+ 0.5+ ],+ "pads": 28,+ "span_mm": 8.9,+ "dash_mm": 0.2225,+ "gap_mm": 0.1335,+ "pad_stroke_mm": 0.0534+ },+ "silkscreen": {+ "material": "Silkscreen reference lines - 30 percent opacity",+ "rgba": [+ 0.92,+ 0.96,+ 1.0,+ 0.3+ ],+ "footprint_items": 7,+ "pin1": {+ "source": "footprint silkscreen",+ "pad": "1"+ }+ },+ "signal_names": {+ "material": "Signal names - 50 percent opacity",+ "rgba": [+ 0.92,+ 0.96,+ 1.0,+ 0.5+ ],+ "font": "DejaVu Sans Mono",+ "labels": 28,+ "sides": "top + mirrored underside (single-sided)",+ "omitted": null,+ "fallback_to_pad_number": 0+ }+ },+ "align": {+ "ok": true,+ "board_underside": true,+ "electrical_pads_without_contact": [],+ "mounting_pads_left_out": [],+ "centre_offset_mm": 0.0,+ "over_pads": true,+ "tolerance_mm": 0.712,+ "orientation_flipped": false,+ "contacts_bbox_mm": [+ -3.9,+ 3.9,+ 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dac8814icdbr.kicad_sym+4−4@@ -20,7 +20,7 @@ (name "VREFA" (effects (font (size 1.27 1.27)))) (number "3" (effects (font (size 1.27 1.27)))) )- (pin passive line (at -17.78 7.62 0) (length 5.08)+ (pin input line (at -17.78 7.62 0) (length 5.08) (name "RFBA" (effects (font (size 1.27 1.27)))) (number "4" (effects (font (size 1.27 1.27)))) )@@ -48,7 +48,7 @@ (name "SDI" (effects (font (size 1.27 1.27)))) (number "10" (effects (font (size 1.27 1.27)))) )- (pin passive line (at -17.78 -10.16 0) (length 5.08)+ (pin input line (at -17.78 -10.16 0) (length 5.08) (name "RFBB" (effects (font (size 1.27 1.27)))) (number "11" (effects (font (size 1.27 1.27)))) )@@ -76,7 +76,7 @@ (name "VREFD" (effects (font (size 1.27 1.27)))) (number "26" (effects (font (size 1.27 1.27)))) )- (pin passive line (at 17.78 7.62 180) (length 5.08)+ (pin input line (at 17.78 7.62 180) (length 5.08) (name "RFBD" (effects (font (size 1.27 1.27)))) (number "25" (effects (font (size 1.27 1.27)))) )@@ -104,7 +104,7 @@ (name "NC" (effects (font (size 1.27 1.27)))) (number "19" (effects (font (size 1.27 1.27)))) )- (pin passive line (at 17.78 -10.16 180) (length 5.08)+ (pin input line (at 17.78 -10.16 180) (length 5.08) (name "RFBC" (effects (font (size 1.27 1.27)))) (number "18" (effects (font (size 1.27 1.27)))) )
dac8814icdbr.lbr+4−4@@ -116,28 +116,28 @@ <pin name="AGNDA" x="-17.78" y="15.24" length="middle" direction="pwr"/> <pin name="IOUTA" x="-17.78" y="12.7" length="middle" direction="out"/> <pin name="VREFA" x="-17.78" y="10.16" length="middle" direction="in"/>- <pin name="RFBA" x="-17.78" y="7.62" length="middle" direction="pas"/>+ <pin name="RFBA" x="-17.78" y="7.62" length="middle" direction="in"/> <pin name="MSB" x="-17.78" y="5.08" length="middle" direction="in"/> <pin name="RS" x="-17.78" y="2.54" length="middle" direction="in"/> <pin name="VDD" x="-17.78" y="0" length="middle" direction="pwr"/> <pin name="CS" x="-17.78" y="-2.54" length="middle" direction="in"/> <pin name="CLK" x="-17.78" y="-5.08" length="middle" direction="in"/> <pin name="SDI" x="-17.78" y="-7.62" length="middle" direction="in"/>- <pin name="RFBB" x="-17.78" y="-10.16" length="middle" direction="pas"/>+ <pin name="RFBB" x="-17.78" y="-10.16" length="middle" direction="in"/> <pin name="VREFB" x="-17.78" y="-12.7" length="middle" direction="in"/> <pin name="IOUTB" x="-17.78" y="-15.24" length="middle" direction="out"/> <pin name="AGNDB" x="-17.78" y="-17.78" length="middle" direction="pwr"/> <pin name="AGNDD" x="17.78" y="15.24" length="middle" direction="pwr" rot="R180"/> <pin name="IOUTD" x="17.78" y="12.7" length="middle" direction="out" rot="R180"/> <pin name="VREFD" x="17.78" y="10.16" length="middle" direction="in" rot="R180"/>- <pin name="RFBD" x="17.78" y="7.62" length="middle" direction="pas" rot="R180"/>+ <pin name="RFBD" x="17.78" y="7.62" length="middle" direction="in" rot="R180"/> <pin name="DGND" x="17.78" y="5.08" length="middle" direction="pwr" rot="R180"/> <pin name="VSS" x="17.78" y="2.54" length="middle" direction="pwr" rot="R180"/> <pin name="AGNDF" x="17.78" y="0" length="middle" direction="pwr" rot="R180"/> <pin name="LDAC" x="17.78" y="-2.54" length="middle" direction="in" rot="R180"/> <pin name="SDO" x="17.78" y="-5.08" length="middle" direction="out" rot="R180"/> <pin name="NC" x="17.78" y="-7.62" length="middle" direction="nc" rot="R180"/>- <pin name="RFBC" x="17.78" y="-10.16" length="middle" direction="pas" rot="R180"/>+ <pin name="RFBC" x="17.78" y="-10.16" length="middle" direction="in" rot="R180"/> <pin name="VREFC" x="17.78" y="-12.7" length="middle" direction="in" rot="R180"/> <pin name="IOUTC" x="17.78" y="-15.24" length="middle" direction="out" rot="R180"/> <pin name="AGNDC" x="17.78" y="-17.78" length="middle" direction="pwr" rot="R180"/>
docs/dac8814icdbr-datasheet.pdf⋯ 1 unchanged line ⋯
package.json+41−41@@ -1,6 +1,6 @@ { "slug": "dac8814icdbr",- "version": "0.1.0",+ "version": "0.1.1", "type": "component", "description": "Texas Instruments Digital To Analog Converters (DACs), SSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.", "tags": [@@ -38,7 +38,7 @@ "pin_count": 28, "category": "Data Converters", "subcategory": "Digital To Analog Converters (DACs)",- "datasheet": "https://www.ti.com/lit/ds/symlink/dac8814icdbr.pdf",+ "datasheet": "https://www.ti.com/lit/ds/symlink/dac8814.pdf", "parts": { "symbol": "dac8814icdbr.kicad_sym", "footprint": "dac8814icdbr.kicad_mod",@@ -54,7 +54,7 @@ "mouser": "595-DAC8814ICDBR" }, "distributor_check": {- "checked_at": "2026-11-12T04:58:44Z",+ "checked_at": "2026-11-12T07:59:37Z", "source": "Component Ocean /api/assign-pns", "digikey": { "pn": "DAC8814ICDBR-ND",@@ -70,109 +70,109 @@ "number": "1", "name": "AGNDA", "type": "power_in",- "description": "DAC A analog ground."+ "description": "DAC A analog ground; the datasheet recommends connecting all AGNDX pins directly to an analog ground plane at the unit." }, { "number": "2", "name": "IOUTA", "type": "output",- "description": "DAC A current output."+ "description": "DAC A current output, whose full-scale value is set by the reference voltage on VREFA (2 mA full-scale current)." }, { "number": "3", "name": "VREFA", "type": "input",- "description": "DAC A reference voltage input that establishes the DAC A full-scale output and can be tied to VDD."+ "description": "DAC A reference voltage input that establishes the full-scale output voltage; it can be tied to VDD." }, { "number": "4", "name": "RFBA",- "type": "passive",- "description": "DAC A feedback resistor terminal that sets the output voltage by connecting to the external amplifier output."+ "type": "input",+ "description": "DAC A feedback resistor connection that establishes the output voltage when connected to the external amplifier output." }, { "number": "5", "name": "MSB", "type": "input",- "description": "MSB bit set during a reset pulse (RS) or at system power-on, tied to ground or VDD, selecting zero-scale (0) or half-scale 8000h (1)."+ "description": "Sets the code loaded by a reset pulse (RS) or at power-on: tied to ground loads zero code, tied to VDD loads half-scale (8000h)." }, { "number": "6", "name": "RS", "type": "input",- "description": "Active-low reset that sets the input and DAC registers to all zeros or half-scale code (8000h) according to the MSB pin voltage."+ "description": "Active-low reset that forces the input and DAC registers to zero code or half-scale code as selected by MSB; may be tied high if not used." }, { "number": "7", "name": "VDD", "type": "power_in",- "description": "Positive power-supply input with a specified operating range of +2.7 V to +5.5 V."+ "description": "Positive power supply input with a specified operating range of +2.7 V to +5.5 V." }, { "number": "8", "name": "CS", "type": "input",- "description": "Active-low chip select that disables shift register loading when high and transfers shift register data to the input register when CS goes high."+ "description": "Active-low chip select that disables shift register loading when high and transfers shift register data to the input register on its rising edge." }, { "number": "9", "name": "CLK", "type": "input",- "description": "Clock input where the positive edge clocks data into the shift register."+ "description": "Clock input; data is clocked into the shift register on the positive edge (SPI-compatible interface rated to 50 MHz)." }, { "number": "10", "name": "SDI", "type": "input",- "description": "Serial data input that loads directly into the shift register."+ "description": "Serial data input; data loads directly into the shift register." }, { "number": "11", "name": "RFBB",- "type": "passive",- "description": "DAC B feedback resistor terminal that sets the output voltage by connecting to the external amplifier output."+ "type": "input",+ "description": "DAC B feedback resistor connection that establishes the output voltage when connected to the external amplifier output." }, { "number": "12", "name": "VREFB", "type": "input",- "description": "DAC B reference voltage input that establishes the DAC B full-scale output and can be tied to VDD."+ "description": "DAC B reference voltage input that establishes the full-scale output voltage; it can be tied to VDD." }, { "number": "13", "name": "IOUTB", "type": "output",- "description": "DAC B current output."+ "description": "DAC B current output, whose full-scale value is set by the reference voltage on VREFB." }, { "number": "14", "name": "AGNDB", "type": "power_in",- "description": "DAC B analog ground."+ "description": "DAC B analog ground; the datasheet recommends connecting all AGNDX pins directly to an analog ground plane at the unit." }, { "number": "15", "name": "AGNDC", "type": "power_in",- "description": "DAC C analog ground."+ "description": "DAC C analog ground; the datasheet recommends connecting all AGNDX pins directly to an analog ground plane at the unit." }, { "number": "16", "name": "IOUTC", "type": "output",- "description": "DAC C current output."+ "description": "DAC C current output, whose full-scale value is set by the reference voltage on VREFC." }, { "number": "17", "name": "VREFC", "type": "input",- "description": "DAC C reference voltage input that establishes the DAC C full-scale output and can be tied to VDD."+ "description": "DAC C reference voltage input that establishes the full-scale output voltage; it can be tied to VDD." }, { "number": "18", "name": "RFBC",- "type": "passive",- "description": "DAC C feedback resistor terminal that sets the output voltage by connecting to the external amplifier output."+ "type": "input",+ "description": "DAC C feedback resistor connection that establishes the output voltage when connected to the external amplifier output." }, { "number": "19",@@ -184,25 +184,25 @@ "number": "20", "name": "SDO", "type": "output",- "description": "Serial data output where data appears 19 clock pulses after input at the SDI pin, allowing daisy-chaining."+ "description": "Serial data output for daisy-chaining; data appears 19 clock pulses after the input at SDI." }, { "number": "21", "name": "LDAC", "type": "input",- "description": "Asynchronous, level-sensitive active-low load strobe that transfers all input register data to the DAC registers."+ "description": "Level-sensitive active-low asynchronous strobe that transfers all input register data to the DAC registers." }, { "number": "22", "name": "AGNDF", "type": "power_in",- "description": "High current analog force ground."+ "description": "High-current analog force ground." }, { "number": "23", "name": "VSS", "type": "power_in",- "description": "No internal connection."+ "description": "Listed as having no internal connection in the pin description table." }, { "number": "24",@@ -213,26 +213,26 @@ { "number": "25", "name": "RFBD",- "type": "passive",- "description": "DAC D feedback resistor terminal that sets the output voltage by connecting to the external amplifier output."+ "type": "input",+ "description": "DAC D feedback resistor connection that establishes the output voltage when connected to the external amplifier output." }, { "number": "26", "name": "VREFD", "type": "input",- "description": "DAC D reference voltage input that establishes the DAC D full-scale output and can be tied to VDD."+ "description": "DAC D reference voltage input that establishes the full-scale output voltage; it can be tied to VDD." }, { "number": "27", "name": "IOUTD", "type": "output",- "description": "DAC D current output."+ "description": "DAC D current output, whose full-scale value is set by the reference voltage on VREFD." }, { "number": "28", "name": "AGNDD", "type": "power_in",- "description": "DAC D analog ground."+ "description": "DAC D analog ground; the datasheet recommends connecting all AGNDX pins directly to an analog ground plane at the unit." } ], "provenance": {@@ -240,22 +240,22 @@ "factory_chain": { "factory": "2.0.0", "extractor": "extract_pins 0.3",- "primary_model": "claude-sonnet-5-5",+ "primary_model": "claude-haiku-5-5", "primary_mode": "text", "consensus_model": "claude-sonnet-5-5", "consensus": "agreed", "guards": "pin_guards 0.1: passed", "guard_notes": [- "extractor flagged: Pin numbers 15-28 were mapped from the DB package top-view figure (right side runs 28 down to 15) an; The datasheet does not give electrical types. IOUTx are set to output and RFBx to passive, which is ; The datasheet says VSS has no internal connection, so it is marked unconnected. The page 5 footnote "+ "extractor flagged: Pin 23 is named VSS but the pin description table says 'No internal connection'. I set its type to p; The datasheet does not give an electrical type for the RFB pins. I classified them as input because ; The datasheet does not give a KiCad type for the analog ground pins. I classified them as power_in p" ], "pages_sent": 11,- "cost_usd": 0.1289,- "at": "2026-11-12T04:58:21"+ "cost_usd": 0.0705,+ "at": "2026-11-12T07:59:01" }, "datasheet": {- "url": "https://www.ti.com/lit/ds/symlink/dac8814icdbr.pdf",+ "url": "https://www.ti.com/lit/ds/symlink/dac8814.pdf", "pages": 30,- "sha256": "3c2f9c3850224afa",+ "sha256": "ac0123b387c7c750", "source_tier": "mfr" }, "cad": "KiCad official (CC-BY-SA 4.0)",@@ -305,13 +305,13 @@ "zmin_mm": 0.0, "centre_offset_mm": 0.0, "footprint_binding": "identity",- "sha256": "ea5ae890f8b27fbe58a13f62721f3f7161ff788d447e15f6a49084b35624fe2c",+ "sha256": "5614c8e5bbf5f03b215fcc23cf10ddf5fc3fc0c8aa4707e1805c9f1c5c5b5963", "checked": "2026-11-12", "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)" } ], "package_dims": {- "package_code": "DB0028A",+ "package_code": "DB (DB0028A, SSOP-28)", "source_page": 27, "D": { "nom_mm": 10.2,
page.json+44−42@@ -4,7 +4,7 @@ "slug": "dac8814icdbr", "title": "DAC8814ICDBR", "brief": "Texas Instruments Digital To Analog Converters (DACs), SSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.1.1", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -20,7 +20,7 @@ "pin_count": 28, "category": "Data Converters", "subcategory": "Digital To Analog Converters (DACs)",- "datasheet": "https://www.ti.com/lit/ds/symlink/dac8814icdbr.pdf",+ "datasheet": "https://www.ti.com/lit/ds/symlink/dac8814.pdf", "parts": { "symbol": "dac8814icdbr.kicad_sym", "footprint": "dac8814icdbr.kicad_mod",@@ -36,7 +36,7 @@ "mouser": "595-DAC8814ICDBR" }, "distributor_check": {- "checked_at": "2026-11-12T04:58:44Z",+ "checked_at": "2026-11-12T07:59:37Z", "source": "Component Ocean /api/assign-pns", "digikey": { "pn": "DAC8814ICDBR-ND",@@ -52,109 +52,109 @@ "number": "1", "name": "AGNDA", "type": "power_in",- "description": "DAC A analog ground."+ "description": "DAC A analog ground; the datasheet recommends connecting all AGNDX pins directly to an analog ground plane at the unit." }, { "number": "2", "name": "IOUTA", "type": "output",- "description": "DAC A current output."+ "description": "DAC A current output, whose full-scale value is set by the reference voltage on VREFA (2 mA full-scale current)." }, { "number": "3", "name": "VREFA", "type": "input",- "description": "DAC A reference voltage input that establishes the DAC A full-scale output and can be tied to VDD."+ "description": "DAC A reference voltage input that establishes the full-scale output voltage; it can be tied to VDD." }, { "number": "4", "name": "RFBA",- "type": "passive",- "description": "DAC A feedback resistor terminal that sets the output voltage by connecting to the external amplifier output."+ "type": "input",+ "description": "DAC A feedback resistor connection that establishes the output voltage when connected to the external amplifier output." }, { "number": "5", "name": "MSB", "type": "input",- "description": "MSB bit set during a reset pulse (RS) or at system power-on, tied to ground or VDD, selecting zero-scale (0) or half-scale 8000h (1)."+ "description": "Sets the code loaded by a reset pulse (RS) or at power-on: tied to ground loads zero code, tied to VDD loads half-scale (8000h)." }, { "number": "6", "name": "RS", "type": "input",- "description": "Active-low reset that sets the input and DAC registers to all zeros or half-scale code (8000h) according to the MSB pin voltage."+ "description": "Active-low reset that forces the input and DAC registers to zero code or half-scale code as selected by MSB; may be tied high if not used." }, { "number": "7", "name": "VDD", "type": "power_in",- "description": "Positive power-supply input with a specified operating range of +2.7 V to +5.5 V."+ "description": "Positive power supply input with a specified operating range of +2.7 V to +5.5 V." }, { "number": "8", "name": "CS", "type": "input",- "description": "Active-low chip select that disables shift register loading when high and transfers shift register data to the input register when CS goes high."+ "description": "Active-low chip select that disables shift register loading when high and transfers shift register data to the input register on its rising edge." }, { "number": "9", "name": "CLK", "type": "input",- "description": "Clock input where the positive edge clocks data into the shift register."+ "description": "Clock input; data is clocked into the shift register on the positive edge (SPI-compatible interface rated to 50 MHz)." }, { "number": "10", "name": "SDI", "type": "input",- "description": "Serial data input that loads directly into the shift register."+ "description": "Serial data input; data loads directly into the shift register." }, { "number": "11", "name": "RFBB",- "type": "passive",- "description": "DAC B feedback resistor terminal that sets the output voltage by connecting to the external amplifier output."+ "type": "input",+ "description": "DAC B feedback resistor connection that establishes the output voltage when connected to the external amplifier output." }, { "number": "12", "name": "VREFB", "type": "input",- "description": "DAC B reference voltage input that establishes the DAC B full-scale output and can be tied to VDD."+ "description": "DAC B reference voltage input that establishes the full-scale output voltage; it can be tied to VDD." }, { "number": "13", "name": "IOUTB", "type": "output",- "description": "DAC B current output."+ "description": "DAC B current output, whose full-scale value is set by the reference voltage on VREFB." }, { "number": "14", "name": "AGNDB", "type": "power_in",- "description": "DAC B analog ground."+ "description": "DAC B analog ground; the datasheet recommends connecting all AGNDX pins directly to an analog ground plane at the unit." }, { "number": "15", "name": "AGNDC", "type": "power_in",- "description": "DAC C analog ground."+ "description": "DAC C analog ground; the datasheet recommends connecting all AGNDX pins directly to an analog ground plane at the unit." }, { "number": "16", "name": "IOUTC", "type": "output",- "description": "DAC C current output."+ "description": "DAC C current output, whose full-scale value is set by the reference voltage on VREFC." }, { "number": "17", "name": "VREFC", "type": "input",- "description": "DAC C reference voltage input that establishes the DAC C full-scale output and can be tied to VDD."+ "description": "DAC C reference voltage input that establishes the full-scale output voltage; it can be tied to VDD." }, { "number": "18", "name": "RFBC",- "type": "passive",- "description": "DAC C feedback resistor terminal that sets the output voltage by connecting to the external amplifier output."+ "type": "input",+ "description": "DAC C feedback resistor connection that establishes the output voltage when connected to the external amplifier output." }, { "number": "19",@@ -166,25 +166,25 @@ "number": "20", "name": "SDO", "type": "output",- "description": "Serial data output where data appears 19 clock pulses after input at the SDI pin, allowing daisy-chaining."+ "description": "Serial data output for daisy-chaining; data appears 19 clock pulses after the input at SDI." }, { "number": "21", "name": "LDAC", "type": "input",- "description": "Asynchronous, level-sensitive active-low load strobe that transfers all input register data to the DAC registers."+ "description": "Level-sensitive active-low asynchronous strobe that transfers all input register data to the DAC registers." }, { "number": "22", "name": "AGNDF", "type": "power_in",- "description": "High current analog force ground."+ "description": "High-current analog force ground." }, { "number": "23", "name": "VSS", "type": "power_in",- "description": "No internal connection."+ "description": "Listed as having no internal connection in the pin description table." }, { "number": "24",@@ -195,26 +195,26 @@ { "number": "25", "name": "RFBD",- "type": "passive",- "description": "DAC D feedback resistor terminal that sets the output voltage by connecting to the external amplifier output."+ "type": "input",+ "description": "DAC D feedback resistor connection that establishes the output voltage when connected to the external amplifier output." }, { "number": "26", "name": "VREFD", "type": "input",- "description": "DAC D reference voltage input that establishes the DAC D full-scale output and can be tied to VDD."+ "description": "DAC D reference voltage input that establishes the full-scale output voltage; it can be tied to VDD." }, { "number": "27", "name": "IOUTD", "type": "output",- "description": "DAC D current output."+ "description": "DAC D current output, whose full-scale value is set by the reference voltage on VREFD." }, { "number": "28", "name": "AGNDD", "type": "power_in",- "description": "DAC D analog ground."+ "description": "DAC D analog ground; the datasheet recommends connecting all AGNDX pins directly to an analog ground plane at the unit." } ], "provenance": {@@ -222,22 +222,22 @@ "factory_chain": { "factory": "2.0.0", "extractor": "extract_pins 0.3",- "primary_model": "claude-sonnet-5-5",+ "primary_model": "claude-haiku-5-5", "primary_mode": "text", "consensus_model": "claude-sonnet-5-5", "consensus": "agreed", "guards": "pin_guards 0.1: passed", "guard_notes": [- "extractor flagged: Pin numbers 15-28 were mapped from the DB package top-view figure (right side runs 28 down to 15) an; The datasheet does not give electrical types. IOUTx are set to output and RFBx to passive, which is ; The datasheet says VSS has no internal connection, so it is marked unconnected. The page 5 footnote "+ "extractor flagged: Pin 23 is named VSS but the pin description table says 'No internal connection'. I set its type to p; The datasheet does not give an electrical type for the RFB pins. I classified them as input because ; The datasheet does not give a KiCad type for the analog ground pins. I classified them as power_in p" ], "pages_sent": 11,- "cost_usd": 0.1289,- "at": "2026-11-12T04:58:21"+ "cost_usd": 0.0705,+ "at": "2026-11-12T07:59:01" }, "datasheet": {- "url": "https://www.ti.com/lit/ds/symlink/dac8814icdbr.pdf",+ "url": "https://www.ti.com/lit/ds/symlink/dac8814.pdf", "pages": 30,- "sha256": "3c2f9c3850224afa",+ "sha256": "ac0123b387c7c750", "source_tier": "mfr" }, "cad": "KiCad official (CC-BY-SA 4.0)",@@ -287,13 +287,13 @@ "zmin_mm": 0, "centre_offset_mm": 0, "footprint_binding": "identity",- "sha256": "ea5ae890f8b27fbe58a13f62721f3f7161ff788d447e15f6a49084b35624fe2c",+ "sha256": "5614c8e5bbf5f03b215fcc23cf10ddf5fc3fc0c8aa4707e1805c9f1c5c5b5963", "checked": "2026-11-12", "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)" } ], "package_dims": {- "package_code": "DB0028A",+ "package_code": "DB (DB0028A, SSOP-28)", "source_page": 27, "D": { "nom_mm": 10.2,@@ -1031,5 +1031,7 @@ ], "visibility": { "public": true- }+ },+ "description": "Texas Instruments Digital To Analog Converters (DACs), SSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "org": "adom" }