← Commit history

Initial commit: component/dac8801idgkr

Ray ·5784d61bb5 ·23h ago
2 files changed +243
README.mdadded+44
@@ -0,0 +1,44 @@+# DAC8801IDGKR++**Texas Instruments** · Digital To Analog Converters (DAC) · VSSOP-8++DAC8801IDGKR from Texas Instruments, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLK | input | Clock input; the positive edge clocks data into the serial shift register, with a clock input frequency up to 50 MHz. |+| 2 | SDI | input | Serial data input that loads directly into the shift register MSB first; extra leading bits are ignored. |+| 3 | RFB | passive | Internal matching feedback resistor that connects to the external op amp output. |+| 4 | VREF | power_in | DAC reference input that sets the full-scale voltage, with a constant input resistance versus code and a VREF range of -15 V to 15 V. |+| 5 | IOUT | output | DAC current output that connects to the inverting terminal of an external precision I-to-V op amp, which holds it at virtual GND. |+| 6 | GND | power_in | Analog and digital ground (0 V reference). |+| 7 | VDD | power_in | Positive power supply input, specified for 2.7 V to 5.5 V operation. |+| 8 | CS | input | Active-low chip select; the rising edge transfers the shift register data to the DAC register. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VSSOP-8 |+| Category | Data Acquisition |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `DAC8801IDGKR`+- Footprint: `Package_SO:VSSOP-8_2.3x2mm_P0.5mm`+- 3D model: VSSOP-8 (KiCad packages3D, STEP)+- 3D model files: `dac8801idgkr-etched.step` / `dac8801idgkr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac8801idgkr.step` / `dac8801idgkr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac8801) (24 pp, sha256 `844d06d546260a54`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac8801idgkr-datasheet.pdf)
page.jsonadded+199
@@ -0,0 +1,199 @@+{+  "slug": "dac8801idgkr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Digital To Analog Converters (DAC), VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "data acquisition",+    "dac8801idgkr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "dac8801idgkr.kicad_sym",+    "dac8801idgkr.kicad_mod",+    "dac8801idgkr.glb",+    "dac8801idgkr.step",+    "dac8801idgkr.lbr",+    "docs/hero.png",+    "docs/dac8801idgkr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "dac8801idgkr-hero.glb",+    "dac8801idgkr-hero.overlay.json"+  ],+  "component": {+    "mpn": "DAC8801IDGKR",+    "manufacturer": "Texas Instruments",+    "package": "VSSOP-8",+    "pin_count": 8,+    "category": "Data Acquisition",+    "subcategory": "Digital To Analog Converters (DAC)",+    "datasheet": "https://www.ti.com/cn/lit/gpn/dac8801",+    "parts": {+      "symbol": "dac8801idgkr.kicad_sym",+      "footprint": "dac8801idgkr.kicad_mod",+      "model_3d": "dac8801idgkr-hero.glb",+      "model_3d_plain": "dac8801idgkr.glb",+      "model_3d_step": "dac8801idgkr-etched.step",+      "model_3d_step_plain": "dac8801idgkr.step",+      "lbr": "dac8801idgkr.lbr"+    },+    "distributor_links": {+      "lcsc": "C2862845",+      "digikey": "296-DAC8801IDGKRTR-ND",+      "mouser": "595-DAC8801IDGKR"+    },+    "distributor_check": {+      "checked_at": "2026-10-08T16:29:56Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-DAC8801IDGKRTR-ND",+        "status": "found"+      },+      "mouser": {+        "pn": "595-DAC8801IDGKR",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "CLK",+        "type": "input",+        "description": "Clock input; the positive edge clocks data into the serial shift register, with a clock input frequency up to 50 MHz."+      },+      {+        "number": "2",+        "name": "SDI",+        "type": "input",+        "description": "Serial data input that loads directly into the shift register MSB first; extra leading bits are ignored."+      },+      {+        "number": "3",+        "name": "RFB",+        "type": "passive",+        "description": "Internal matching feedback resistor that connects to the external op amp output."+      },+      {+        "number": "4",+        "name": "VREF",+        "type": "power_in",+        "description": "DAC reference input that sets the full-scale voltage, with a constant input resistance versus code and a VREF range of -15 V to 15 V."+      },+      {+        "number": "5",+        "name": "IOUT",+        "type": "output",+        "description": "DAC current output that connects to the inverting terminal of an external precision I-to-V op amp, which holds it at virtual GND."+      },+      {+        "number": "6",+        "name": "GND",+        "type": "power_in",+        "description": "Analog and digital ground (0 V reference)."+      },+      {+        "number": "7",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive power supply input, specified for 2.7 V to 5.5 V operation."+      },+      {+        "number": "8",+        "name": "CS",+        "type": "input",+        "description": "Active-low chip select; the rising edge transfers the shift register data to the DAC register."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-5-5",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: The DGK top-view pin diagram text in the extracted datasheet is scrambled, so the pin-number-to-name; The DAC8801IDGKR is the 8-lead VSSOP (DGK) variant per the ordering table (page 2) and package adden"+        ],+        "pages_sent": 24,+        "cost_usd": 0.0893,+        "at": "2026-10-08T16:29:40"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/dac8801",+        "pages": 24,+        "sha256": "844d06d546260a54",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 8,+        "described": 8,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "dac8801idgkr.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          3.1,+          2,+          0.85+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "353552981eef35cb93635057d4aeb89aef22648c77af6fd095e328bfe6b834bd",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "dac8801idgkr-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          3.1,+          2,+          0.85+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "421a8c99aa373eb7e69ae2a5f1aadfcbbc1a40ecaf8f13715557bf43d91726df",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file