component
DAC7578SPWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
← Commit history
dac7578spwr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
2 files changed
+94−14
package.json+52−12@@ -71,31 +71,31 @@ "number": "4", "name": "VOUTA", "type": "output",- "description": "Analog output voltage from DAC A, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+ "description": "Analog output voltage from DAC A, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded" }, { "number": "5", "name": "VOUTC", "type": "output",- "description": "Analog output voltage from DAC C, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+ "description": "Analog output voltage from DAC C, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded" }, { "number": "6", "name": "VOUTE", "type": "output",- "description": "Analog output voltage from DAC E, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+ "description": "Analog output voltage from DAC E, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded" }, { "number": "7", "name": "VOUTG", "type": "output",- "description": "Analog output voltage from DAC G, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+ "description": "Analog output voltage from DAC G, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded" }, { "number": "8", "name": "VREFIN", "type": "input",- "description": "Positive external reference input, 0V to 5V for scaling DAC output range with typical external reference current 60\u00b5A"+ "description": "Positive external reference input, 0V to 5V for scaling DAC output range with typical external reference current 60µA" }, { "number": "9",@@ -107,25 +107,25 @@ "number": "10", "name": "VOUTH", "type": "output",- "description": "Analog output voltage from DAC H, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+ "description": "Analog output voltage from DAC H, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded" }, { "number": "11", "name": "VOUTF", "type": "output",- "description": "Analog output voltage from DAC F, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+ "description": "Analog output voltage from DAC F, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded" }, { "number": "12", "name": "VOUTD", "type": "output",- "description": "Analog output voltage from DAC D, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+ "description": "Analog output voltage from DAC D, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded" }, { "number": "13", "name": "VOUTB", "type": "output",- "description": "Analog output voltage from DAC B, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+ "description": "Analog output voltage from DAC B, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded" }, { "number": "14",@@ -137,7 +137,7 @@ "number": "15", "name": "SDA", "type": "bidirectional",- "description": "I2C bidirectional open-drain serial data line with external pull-up resistor (1k\u03a9 to 10k\u03a9 recommended), supports up to 3.4MHz clock rate"+ "description": "I2C bidirectional open-drain serial data line with external pull-up resistor (1kΩ to 10kΩ recommended), supports up to 3.4MHz clock rate" }, { "number": "16",@@ -178,6 +178,46 @@ "viewers": { "symbol": "viewers/symbol.html", "footprint": "viewers/footprint.html"- }+ },+ "models_3d": [+ {+ "file": "dac7578spwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5.0,+ 1.1+ ],+ "zmin_mm": -0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dac7578spwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5.0,+ 1.1+ ],+ "zmin_mm": -0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "0227725bcc74f5b30efc9f6f956927b0b4815ac7a0ea799a913908b06b12f0b0",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ] }-}+}
page.json+42−2@@ -163,7 +163,47 @@ "viewers": { "symbol": "viewers/symbol.html", "footprint": "viewers/footprint.html"- }+ },+ "models_3d": [+ {+ "file": "dac7578spwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5.0,+ 1.1+ ],+ "zmin_mm": -0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dac7578spwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5.0,+ 1.1+ ],+ "zmin_mm": -0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "0227725bcc74f5b30efc9f6f956927b0b4815ac7a0ea799a913908b06b12f0b0",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ] }, "metadata": { "specs": {@@ -210,4 +250,4 @@ "visibility": { "public": true }-}+}