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Set visibility: public

Ray ·2ce8d57c52 · ·parent 1b4f02f
1 file changed +14−11
page.json+14−11
@@ -56,31 +56,31 @@         "number": "4",         "name": "VOUTA",         "type": "output",-        "description": "Analog output voltage from DAC A, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+        "description": "Analog output voltage from DAC A, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded"       },       {         "number": "5",         "name": "VOUTC",         "type": "output",-        "description": "Analog output voltage from DAC C, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+        "description": "Analog output voltage from DAC C, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded"       },       {         "number": "6",         "name": "VOUTE",         "type": "output",-        "description": "Analog output voltage from DAC E, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+        "description": "Analog output voltage from DAC E, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded"       },       {         "number": "7",         "name": "VOUTG",         "type": "output",-        "description": "Analog output voltage from DAC G, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+        "description": "Analog output voltage from DAC G, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded"       },       {         "number": "8",         "name": "VREFIN",         "type": "input",-        "description": "Positive external reference input, 0V to 5V for scaling DAC output range with typical external reference current 60\u00b5A"+        "description": "Positive external reference input, 0V to 5V for scaling DAC output range with typical external reference current 60µA"       },       {         "number": "9",@@ -92,25 +92,25 @@         "number": "10",         "name": "VOUTH",         "type": "output",-        "description": "Analog output voltage from DAC H, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+        "description": "Analog output voltage from DAC H, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded"       },       {         "number": "11",         "name": "VOUTF",         "type": "output",-        "description": "Analog output voltage from DAC F, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+        "description": "Analog output voltage from DAC F, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded"       },       {         "number": "12",         "name": "VOUTD",         "type": "output",-        "description": "Analog output voltage from DAC D, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+        "description": "Analog output voltage from DAC D, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded"       },       {         "number": "13",         "name": "VOUTB",         "type": "output",-        "description": "Analog output voltage from DAC B, 0V to AVDD, 0.75V/\u03bcs slew rate, 7\u03bcs settling time unloaded"+        "description": "Analog output voltage from DAC B, 0V to AVDD, 0.75V/μs slew rate, 7μs settling time unloaded"       },       {         "number": "14",@@ -122,7 +122,7 @@         "number": "15",         "name": "SDA",         "type": "bidirectional",-        "description": "I2C bidirectional open-drain serial data line with external pull-up resistor (1k\u03a9 to 10k\u03a9 recommended), supports up to 3.4MHz clock rate"+        "description": "I2C bidirectional open-drain serial data line with external pull-up resistor (1kΩ to 10kΩ recommended), supports up to 3.4MHz clock rate"       },       {         "number": "16",@@ -206,5 +206,8 @@     "docs/dac7578spwr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file