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DAC71416RHAR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+78@@ -0,0 +1,78 @@+# DAC71416RHAR++**Texas Instruments** · Digital To Analog Converters (DAC) · VQFN-40-EP(6x6)++DAC71416RHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OUT0 | output | Channel 0 analog DAC output voltage. |+| 2 | OUT1 | output | Channel 1 analog DAC output voltage. |+| 3 | OUT2 | output | Channel 2 analog DAC output voltage. |+| 4 | OUT3 | output | Channel 3 analog DAC output voltage. |+| 5 | OUT4 | output | Channel 4 analog DAC output voltage. |+| 6 | OUT5 | output | Channel 5 analog DAC output voltage. |+| 7 | OUT6 | output | Channel 6 analog DAC output voltage. |+| 8 | OUT7 | output | Channel 7 analog DAC output voltage. |+| 9 | VIO | power_in | IO supply voltage, 1.7 V to 5.5 V; sets the logic levels of the digital inputs and outputs. |+| 10 | GND | power_in | Ground reference point for all circuits in the device. |+| 11 | SDO | output | Serial interface data output, enabled by the SDO-EN bit; data shifts out on the SCLK rising or falling edge as set by FSDO (default rising edge), and the pin is high-impedance when CS is high. |+| 12 | SCLK | input | Serial interface clock input. |+| 13 | SDI | input | Serial interface data input; data is shifted into the input shift register on each falling edge of SCLK. |+| 14 | CS | input | Active-low serial data enable and frame sync; the serial interface input shift register is enabled when CS goes low. |+| 15 | TOGGLE0 | input | Toggle control 0 for DACs configured for toggle mode: low selects register A and high selects register B; tie to GND if unused. |+| 16 | TOGGLE1 | input | Toggle control 1 for DACs configured for toggle mode: low selects register A and high selects register B; tie to GND if unused. |+| 17 | TOGGLE2 | input | Toggle control 2 for DACs configured for toggle mode: low selects register A and high selects register B; tie to GND if unused. |+| 18 | LDAC | input | Active-low synchronous update signal that updates all DAC outputs configured for synchronous mode at once; connect to VIO if unused. |+| 19 | RESET | input | Active-low reset input; a logic low of at least 500 ns starts a hardware reset (POR event). |+| 20 | CLR | input | Active-low clear input that forces all DAC outputs to their clear code; connect to VIO if unused. |+| 21 | ALMOUT | output | Open-drain alarm output that requires an external 10 kΩ pull-up to a voltage no greater than VIO. |+| 22 | TEMPOUT | output | Analog temperature monitor output with a sensor gain of -4 mV/°C and a 1.34 V offset at 0 °C. |+| 23 | OUT8 | output | Channel 8 analog DAC output voltage. |+| 24 | OUT9 | output | Channel 9 analog DAC output voltage. |+| 25 | OUT10 | output | Channel 10 analog DAC output voltage. |+| 26 | OUT11 | output | Channel 11 analog DAC output voltage. |+| 27 | OUT12 | output | Channel 12 analog DAC output voltage. |+| 28 | OUT13 | output | Channel 13 analog DAC output voltage. |+| 29 | OUT14 | output | Channel 14 analog DAC output voltage. |+| 30 | OUT15 | output | Channel 15 analog DAC output voltage. |+| 31 | VCC | power_in | Positive analog supply for the output amplifiers, 9 V to 41.5 V. |+| 32 | VSS | power_in | Negative analog supply for the output amplifiers, -21.5 V to 0 V. |+| 33 | REF | bidirectional | Reference input when using an external reference; reference output when the internal reference is used, which requires a 150 nF capacitor to GND. |+| 34 | REFCMP | bidirectional | Reference compensation capacitor connection; a 330 pF capacitor is connected between REFCMP and REFGND. |+| 35 | REFGND | power_in | Ground reference point for the internal reference. |+| 36 | GND | power_in | Ground reference point for all circuits in the device. |+| 37 | VAA | power_in | Analog supply voltage, 4.5 V to 5.5 V; must be at the same potential as VDD. |+| 38 | VDD | power_in | Digital supply voltage, 4.5 V to 5.5 V; must be at the same potential as VAA. |+| 39 | VSS | power_in | Negative analog supply for the output amplifiers, -21.5 V to 0 V. |+| 40 | VCC | power_in | Positive analog supply for the output amplifiers, 9 V to 41.5 V. |+| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-40-EP(6x6) |+| Category | Data Acquisition |+| Pins | 41 |++## CAD (KiCad official)++- Symbol: `DAC71416RHAR`+- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`+- 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)+- 3D model files: `dac71416rhar-etched.step` / `dac71416rhar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac71416rhar.step` / `dac71416rhar.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac71416) (64 pp, sha256 `78fbb0be664f4e12`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac71416rhar-datasheet.pdf)
page.jsonadded+399@@ -0,0 +1,399 @@+{+ "slug": "dac71416rhar",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Digital To Analog Converters (DAC), VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "dac71416rhar",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dac71416rhar.kicad_sym",+ "dac71416rhar.kicad_mod",+ "dac71416rhar.glb",+ "dac71416rhar.step",+ "dac71416rhar.lbr",+ "docs/hero.png",+ "docs/dac71416rhar-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "dac71416rhar-hero.glb",+ "dac71416rhar-hero.overlay.json"+ ],+ "component": {+ "mpn": "DAC71416RHAR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-40-EP(6x6)",+ "pin_count": 41,+ "category": "Data Acquisition",+ "subcategory": "Digital To Analog Converters (DAC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dac71416",+ "parts": {+ "symbol": "dac71416rhar.kicad_sym",+ "footprint": "dac71416rhar.kicad_mod",+ "model_3d": "dac71416rhar-hero.glb",+ "model_3d_plain": "dac71416rhar.glb",+ "model_3d_step": "dac71416rhar-etched.step",+ "model_3d_step_plain": "dac71416rhar.step",+ "lbr": "dac71416rhar.lbr"+ },+ "distributor_links": {+ "lcsc": "C2680097",+ "digikey": "296-DAC71416RHARTR-ND",+ "mouser": "595-DAC71416RHAR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T21:29:30Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-DAC71416RHARTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DAC71416RHAR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "OUT0",+ "type": "output",+ "description": "Channel 0 analog DAC output voltage."+ },+ {+ "number": "2",+ "name": "OUT1",+ "type": "output",+ "description": "Channel 1 analog DAC output voltage."+ },+ {+ "number": "3",+ "name": "OUT2",+ "type": "output",+ "description": "Channel 2 analog DAC output voltage."+ },+ {+ "number": "4",+ "name": "OUT3",+ "type": "output",+ "description": "Channel 3 analog DAC output voltage."+ },+ {+ "number": "5",+ "name": "OUT4",+ "type": "output",+ "description": "Channel 4 analog DAC output voltage."+ },+ {+ "number": "6",+ "name": "OUT5",+ "type": "output",+ "description": "Channel 5 analog DAC output voltage."+ },+ {+ "number": "7",+ "name": "OUT6",+ "type": "output",+ "description": "Channel 6 analog DAC output voltage."+ },+ {+ "number": "8",+ "name": "OUT7",+ "type": "output",+ "description": "Channel 7 analog DAC output voltage."+ },+ {+ "number": "9",+ "name": "VIO",+ "type": "power_in",+ "description": "IO supply voltage, 1.7 V to 5.5 V; sets the logic levels of the digital inputs and outputs."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference point for all circuits in the device."+ },+ {+ "number": "11",+ "name": "SDO",+ "type": "output",+ "description": "Serial interface data output, enabled by the SDO-EN bit; data shifts out on the SCLK rising or falling edge as set by FSDO (default rising edge), and the pin is high-impedance when CS is high."+ },+ {+ "number": "12",+ "name": "SCLK",+ "type": "input",+ "description": "Serial interface clock input."+ },+ {+ "number": "13",+ "name": "SDI",+ "type": "input",+ "description": "Serial interface data input; data is shifted into the input shift register on each falling edge of SCLK."+ },+ {+ "number": "14",+ "name": "CS",+ "type": "input",+ "description": "Active-low serial data enable and frame sync; the serial interface input shift register is enabled when CS goes low."+ },+ {+ "number": "15",+ "name": "TOGGLE0",+ "type": "input",+ "description": "Toggle control 0 for DACs configured for toggle mode: low selects register A and high selects register B; tie to GND if unused."+ },+ {+ "number": "16",+ "name": "TOGGLE1",+ "type": "input",+ "description": "Toggle control 1 for DACs configured for toggle mode: low selects register A and high selects register B; tie to GND if unused."+ },+ {+ "number": "17",+ "name": "TOGGLE2",+ "type": "input",+ "description": "Toggle control 2 for DACs configured for toggle mode: low selects register A and high selects register B; tie to GND if unused."+ },+ {+ "number": "18",+ "name": "LDAC",+ "type": "input",+ "description": "Active-low synchronous update signal that updates all DAC outputs configured for synchronous mode at once; connect to VIO if unused."+ },+ {+ "number": "19",+ "name": "RESET",+ "type": "input",+ "description": "Active-low reset input; a logic low of at least 500 ns starts a hardware reset (POR event)."+ },+ {+ "number": "20",+ "name": "CLR",+ "type": "input",+ "description": "Active-low clear input that forces all DAC outputs to their clear code; connect to VIO if unused."+ },+ {+ "number": "21",+ "name": "ALMOUT",+ "type": "output",+ "description": "Open-drain alarm output that requires an external 10 kΩ pull-up to a voltage no greater than VIO."+ },+ {+ "number": "22",+ "name": "TEMPOUT",+ "type": "output",+ "description": "Analog temperature monitor output with a sensor gain of -4 mV/°C and a 1.34 V offset at 0 °C."+ },+ {+ "number": "23",+ "name": "OUT8",+ "type": "output",+ "description": "Channel 8 analog DAC output voltage."+ },+ {+ "number": "24",+ "name": "OUT9",+ "type": "output",+ "description": "Channel 9 analog DAC output voltage."+ },+ {+ "number": "25",+ "name": "OUT10",+ "type": "output",+ "description": "Channel 10 analog DAC output voltage."+ },+ {+ "number": "26",+ "name": "OUT11",+ "type": "output",+ "description": "Channel 11 analog DAC output voltage."+ },+ {+ "number": "27",+ "name": "OUT12",+ "type": "output",+ "description": "Channel 12 analog DAC output voltage."+ },+ {+ "number": "28",+ "name": "OUT13",+ "type": "output",+ "description": "Channel 13 analog DAC output voltage."+ },+ {+ "number": "29",+ "name": "OUT14",+ "type": "output",+ "description": "Channel 14 analog DAC output voltage."+ },+ {+ "number": "30",+ "name": "OUT15",+ "type": "output",+ "description": "Channel 15 analog DAC output voltage."+ },+ {+ "number": "31",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive analog supply for the output amplifiers, 9 V to 41.5 V."+ },+ {+ "number": "32",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative analog supply for the output amplifiers, -21.5 V to 0 V."+ },+ {+ "number": "33",+ "name": "REF",+ "type": "bidirectional",+ "description": "Reference input when using an external reference; reference output when the internal reference is used, which requires a 150 nF capacitor to GND."+ },+ {+ "number": "34",+ "name": "REFCMP",+ "type": "bidirectional",+ "description": "Reference compensation capacitor connection; a 330 pF capacitor is connected between REFCMP and REFGND."+ },+ {+ "number": "35",+ "name": "REFGND",+ "type": "power_in",+ "description": "Ground reference point for the internal reference."+ },+ {+ "number": "36",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference point for all circuits in the device."+ },+ {+ "number": "37",+ "name": "VAA",+ "type": "power_in",+ "description": "Analog supply voltage, 4.5 V to 5.5 V; must be at the same potential as VDD."+ },+ {+ "number": "38",+ "name": "VDD",+ "type": "power_in",+ "description": "Digital supply voltage, 4.5 V to 5.5 V; must be at the same potential as VAA."+ },+ {+ "number": "39",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative analog supply for the output amplifiers, -21.5 V to 0 V."+ },+ {+ "number": "40",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive analog supply for the output amplifiers, 9 V to 41.5 V."+ },+ {+ "number": "41",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet pin table lists 40 numbered pins plus a thermal pad, but it gives the thermal pad no p; Pins 10 and 36 (GND), 31 and 40 (VCC), and 32 and 39 (VSS) are each listed as a pair in the datashee; The datasheet pin table lists SDO as type 输出 (output), but the text states SDO is high-impedance whe",+ "exposed pad 41 added from the footprint"+ ],+ "pages_sent": 35,+ "cost_usd": 0.1963,+ "at": "2026-10-07T21:29:11"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dac71416",+ "pages": 64,+ "sha256": "78fbb0be664f4e12",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dac71416rhar.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e5b4286c2329085d9ef7f90d5eb5bf41a435241ecc1baaf1383823b6d6a946ae",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dac71416rhar-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4e20c4d00b2fa79039603dc8de09e9d833098c2289ab4df10887b4efda6267fe",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}