component
DAC60508ZRTER
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), WQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
dac60508zrter: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
2 files changed
+95−15
package.json+53−13@@ -59,25 +59,25 @@ "number": "2", "name": "OUT0", "type": "output",- "description": "Analog output voltage from DAC channel 0; output range 0V to VREF, 0V to 2\u00d7VREF, or 0V to \u00bd\u00d7VREF configurable via BUFF-GAIN and REF-DIV bits."+ "description": "Analog output voltage from DAC channel 0; output range 0V to VREF, 0V to 2×VREF, or 0V to ½×VREF configurable via BUFF-GAIN and REF-DIV bits." }, { "number": "3", "name": "OUT1", "type": "output",- "description": "Analog output voltage from DAC channel 1; output range 0V to VREF, 0V to 2\u00d7VREF, or 0V to \u00bd\u00d7VREF configurable via BUFF-GAIN and REF-DIV bits."+ "description": "Analog output voltage from DAC channel 1; output range 0V to VREF, 0V to 2×VREF, or 0V to ½×VREF configurable via BUFF-GAIN and REF-DIV bits." }, { "number": "4", "name": "OUT2", "type": "output",- "description": "Analog output voltage from DAC channel 2; output range 0V to VREF, 0V to 2\u00d7VREF, or 0V to \u00bd\u00d7VREF configurable via BUFF-GAIN and REF-DIV bits."+ "description": "Analog output voltage from DAC channel 2; output range 0V to VREF, 0V to 2×VREF, or 0V to ½×VREF configurable via BUFF-GAIN and REF-DIV bits." }, { "number": "5", "name": "OUT3", "type": "output",- "description": "Analog output voltage from DAC channel 3; output range 0V to VREF, 0V to 2\u00d7VREF, or 0V to \u00bd\u00d7VREF configurable via BUFF-GAIN and REF-DIV bits."+ "description": "Analog output voltage from DAC channel 3; output range 0V to VREF, 0V to 2×VREF, or 0V to ½×VREF configurable via BUFF-GAIN and REF-DIV bits." }, { "number": "6",@@ -89,31 +89,31 @@ "number": "7", "name": "VDD", "type": "power_in",- "description": "Analog supply voltage 2.7V to 5.5V; bypass with 1-10\u00b5F and 0.1\u00b5F capacitors per Power Supply Recommendations section."+ "description": "Analog supply voltage 2.7V to 5.5V; bypass with 1-10µF and 0.1µF capacitors per Power Supply Recommendations section." }, { "number": "8", "name": "OUT4", "type": "output",- "description": "Analog output voltage from DAC channel 4; output range 0V to VREF, 0V to 2\u00d7VREF, or 0V to \u00bd\u00d7VREF configurable via BUFF-GAIN and REF-DIV bits."+ "description": "Analog output voltage from DAC channel 4; output range 0V to VREF, 0V to 2×VREF, or 0V to ½×VREF configurable via BUFF-GAIN and REF-DIV bits." }, { "number": "9", "name": "OUT5", "type": "output",- "description": "Analog output voltage from DAC channel 5; output range 0V to VREF, 0V to 2\u00d7VREF, or 0V to \u00bd\u00d7VREF configurable via BUFF-GAIN and REF-DIV bits."+ "description": "Analog output voltage from DAC channel 5; output range 0V to VREF, 0V to 2×VREF, or 0V to ½×VREF configurable via BUFF-GAIN and REF-DIV bits." }, { "number": "10", "name": "OUT6", "type": "output",- "description": "Analog output voltage from DAC channel 6; output range 0V to VREF, 0V to 2\u00d7VREF, or 0V to \u00bd\u00d7VREF configurable via BUFF-GAIN and REF-DIV bits."+ "description": "Analog output voltage from DAC channel 6; output range 0V to VREF, 0V to 2×VREF, or 0V to ½×VREF configurable via BUFF-GAIN and REF-DIV bits." }, { "number": "11", "name": "OUT7", "type": "output",- "description": "Analog output voltage from DAC channel 7; output range 0V to VREF, 0V to 2\u00d7VREF, or 0V to \u00bd\u00d7VREF configurable via BUFF-GAIN and REF-DIV bits."+ "description": "Analog output voltage from DAC channel 7; output range 0V to VREF, 0V to 2×VREF, or 0V to ½×VREF configurable via BUFF-GAIN and REF-DIV bits." }, { "number": "12",@@ -137,13 +137,13 @@ "number": "15", "name": "SDO/ALARM", "type": "output",- "description": "Serial interface data output (default, high-impedance when CS high) or configurable as open-drain alarm output for CRC or reference error indication (requires 10k\u03a9 pull-up to VIO)."+ "description": "Serial interface data output (default, high-impedance when CS high) or configurable as open-drain alarm output for CRC or reference error indication (requires 10kΩ pull-up to VIO)." }, { "number": "16", "name": "VIO", "type": "power_in",- "description": "I/O supply voltage 1.7V to 5.5V; sets serial interface logic levels and requires 0.1\u00b5F bypass capacitor."+ "description": "I/O supply voltage 1.7V to 5.5V; sets serial interface logic levels and requires 0.1µF bypass capacitor." }, { "number": "17",@@ -187,6 +187,46 @@ "viewers": { "symbol": "viewers/symbol.html", "footprint": "viewers/footprint.html"- }+ },+ "models_3d": [+ {+ "file": "dac60508zrter.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3.0,+ 3.0,+ 0.785+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "3eb81ffac423a66cdcfead8efe56401da171edaf1f2257049aad7b2d3900f6c8",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dac60508zrter-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3.0,+ 3.0,+ 0.785+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "18611ffa5cec2f7afe4e567c5f171e30c90ea02f58e11951b4bd51e5578ed759",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ] }-}+}
page.json+42−2@@ -172,7 +172,47 @@ "viewers": { "symbol": "viewers/symbol.html", "footprint": "viewers/footprint.html"- }+ },+ "models_3d": [+ {+ "file": "dac60508zrter.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3.0,+ 3.0,+ 0.785+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "3eb81ffac423a66cdcfead8efe56401da171edaf1f2257049aad7b2d3900f6c8",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dac60508zrter-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3.0,+ 3.0,+ 0.785+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "18611ffa5cec2f7afe4e567c5f171e30c90ea02f58e11951b4bd51e5578ed759",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ] }, "metadata": { "specs": {@@ -220,4 +260,4 @@ "public": true }, "updated_at": "2026-09-24T19:39:12.993Z"-}+}