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Set visibility: public

Ray ·9875512b68 · ·parent 6528c74
1 file changed +7−4
page.json+7−4
@@ -32,7 +32,7 @@         "number": "1",         "name": "VOUT",         "type": "output",-        "description": "Analog output voltage from the 8-bit DAC. Rail-to-rail buffered output spanning 0 V to VDD driving up to a 2 k\u03a9 / 200 pF load; short-circuit current 50 mA at VDD=5 V."+        "description": "Analog output voltage from the 8-bit DAC. Rail-to-rail buffered output spanning 0 V to VDD driving up to a 2 kΩ / 200 pF load; short-circuit current 50 mA at VDD=5 V."       },       {         "number": "2",@@ -44,7 +44,7 @@         "number": "3",         "name": "VDD",         "type": "power_in",-        "description": "Analog voltage supply input, +2.7 V to +5.5 V. Also sets the full-scale DAC output range (0 V to VDD). Typical IDD 155 \u00b5A at 5 V active, 0.2 \u00b5A in power-down."+        "description": "Analog voltage supply input, +2.7 V to +5.5 V. Also sets the full-scale DAC output range (0 V to VDD). Typical IDD 155 µA at 5 V active, 0.2 µA in power-down."       },       {         "number": "4",@@ -56,7 +56,7 @@         "number": "5",         "name": "SCL",         "type": "input",-        "description": "I2C serial clock input. Referenced to VDD/GND logic thresholds (VIH \u2265 0.7\u00b7VDD, VIL \u2264 0.3\u00b7VDD). Requires external pull-up to VDD."+        "description": "I2C serial clock input. Referenced to VDD/GND logic thresholds (VIH ≥ 0.7·VDD, VIL ≤ 0.3·VDD). Requires external pull-up to VDD."       },       {         "number": "6",@@ -136,5 +136,8 @@     "docs/dac5571idbvr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file