CY8C4024LQI-S402T

@@ -0,0 +1,83 @@+# CY8C4024LQI-S402T++**Infineon Cypress Semicon** · Microcontrollers (MCU/MPU/SOC) · QFN-32(5x5)++CY8C4024LQI-S402T from Infineon Cypress Semicon, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | P1.7 | bidirectional | General-purpose I/O port pin P1.7. CAPSENSE-, analog-, and digital-capable; no dedicated alternate peripheral function is assigned. |+| 2 | P2.0 | bidirectional | GPIO P2.0. Muxed alt functions: prgio[0].io[0] (Smart I/O), tcpwm.line[4], csd.comp, tcpwm.tr_in[4], scb[1].i2c_scl, scb[1].spi_mosi. |+| 3 | P2.1 | bidirectional | GPIO P2.1. Muxed alt functions: prgio[0].io[1], tcpwm.line_compl[4], tcpwm.tr_in[5], scb[1].i2c_sda, scb[1].spi_miso. |+| 4 | P2.2 | bidirectional | GPIO P2.2. Muxed alt functions: prgio[0].io[2], scb[1].spi_clk. |+| 5 | P2.3 | bidirectional | GPIO P2.3. Muxed alt functions: prgio[0].io[3], scb[1].spi_select0. |+| 6 | P2.5 | bidirectional | GPIO P2.5. Muxed alt functions: prgio[0].io[5], tcpwm.line_compl[0], scb[1].spi_select2. |+| 7 | P2.6 | bidirectional | GPIO P2.6. Muxed alt functions: prgio[0].io[6], tcpwm.line[1], scb[1].spi_select3. |+| 8 | P2.7 | bidirectional | GPIO P2.7. Muxed alt functions: prgio[0].io[7], tcpwm.line_compl[1], lpcomp.comp[0]. |+| 9 | P3.0 | bidirectional | GPIO P3.0. Muxed alt functions: prgio[1].io[0], tcpwm.line[0], scb[1].uart_rx, scb[1].i2c_scl, scb[1].spi_mosi. |+| 10 | P3.1 | bidirectional | GPIO P3.1. Muxed alt functions: prgio[1].io[1], tcpwm.line_compl[0], scb[1].uart_tx, scb[1].i2c_sda, scb[1].spi_miso. |+| 11 | P3.2 | bidirectional | GPIO P3.2, default SWD data (SWDIO). Muxed alt functions: prgio[1].io[2], tcpwm.line[1], scb[1].uart_cts, cpuss.swd_data, scb[1].spi_clk. |+| 12 | P3.3 | bidirectional | GPIO P3.3, default SWD clock (SWDCK). Muxed alt functions: prgio[1].io[3], tcpwm.line_compl[1], scb[1].uart_rts, cpuss.swd_clk, scb[1].spi_select0. |+| 13 | P4.0 | bidirectional | GPIO P4.0. Analog: csd.vref_ext. Muxed alt functions: scb[0].uart_rx, tcpwm.tr_in[10], scb[0].i2c_scl, scb[0].spi_mosi. |+| 14 | P4.1 | bidirectional | GPIO P4.1. Analog: csd.cshieldpads. Muxed alt functions: scb[0].uart_tx, tcpwm.tr_in[11], scb[0].i2c_sda, scb[0].spi_miso. |+| 15 | P4.2 | bidirectional | GPIO P4.2. Analog: csd.cmodpad (Cmod capacitor for CAPSENSE CSD). Muxed alt functions: scb[0].uart_cts, lpcomp.comp[0], scb[0].spi_clk. |+| 16 | P4.3 | bidirectional | GPIO P4.3. Analog: csd.csh_tank (Csh tank capacitor for CAPSENSE). Muxed alt functions: scb[0].uart_rts, lpcomp.comp[1], scb[0].spi_select0. |+| 17 | P0.0 | bidirectional | GPIO P0.0. Analog: lpcomp.in_p[0]. Muxed alt functions: tcpwm.tr_in[0], scb[0].spi_select1. |+| 18 | P0.1 | bidirectional | GPIO P0.1. Analog: lpcomp.in_n[0]. Muxed alt functions: tcpwm.tr_in[1], scb[0].spi_select2. |+| 19 | P0.2 | bidirectional | GPIO P0.2. Analog: lpcomp.in_p[1]. Muxed alt function: scb[0].spi_select3. |+| 20 | P0.3 | bidirectional | GPIO P0.3. Analog: lpcomp.in_n[1]. No digital peripheral alternate function assigned. |+| 21 | P0.4 | bidirectional | GPIO P0.4. Analog: wco.wco_in (32.768 kHz Watch Crystal in). Muxed alt functions: scb[1].uart_rx, scb[1].i2c_scl, scb[1].spi_mosi. |+| 22 | P0.5 | bidirectional | GPIO P0.5. Analog: wco.wco_out (32.768 kHz Watch Crystal out). Muxed alt functions: scb[1].uart_tx, scb[1].i2c_sda, scb[1].spi_miso. |+| 23 | P0.6 | bidirectional | GPIO P0.6. Analog: srss.ext_clk (external clock input). Muxed alt functions: scb[1].uart_cts, scb[1].spi_clk. |+| 24 | XRES | input | Active-low external reset input. Internal pull-up to VDDD is always enabled; asserting XRES low forces a full chip reset. |+| 25 | VCCD | passive | Regulated digital core supply, 1.8 V ±5%. Must be bypassed to VSSD with 0.1 uF X5R ceramic. Do not connect to anything else in Mode 1; short to VDD in Mode 2 (external 1.71-1.89 V supply). |+| 26 | VSSD | power_in | Digital ground return. |+| 27 | VDD | power_in | Combined analog + digital supply (VDDA and VDDD tied together on the 32-pin QFN). 1.8-5.5 V in Mode 1 with internal LDO active, or 1.71-1.89 V in Mode 2. Bypass with 1 uF || 0.1 uF to VSS. |+| 28 | VSSA | power_in | Analog ground return. |+| 29 | P1.0 | bidirectional | GPIO P1.0. Muxed alt functions: tcpwm.line[2], scb[0].uart_rx, scb[0].i2c_scl, scb[0].spi_mosi. |+| 30 | P1.1 | bidirectional | GPIO P1.1. Muxed alt functions: tcpwm.line_compl[2], scb[0].uart_tx, scb[0].i2c_sda, scb[0].spi_miso. |+| 31 | P1.2 | bidirectional | GPIO P1.2. Muxed alt functions: tcpwm.line[3], scb[0].uart_cts, tcpwm.tr_in[2], scb[0].spi_clk. |+| 32 | P1.3 | bidirectional | GPIO P1.3. Muxed alt functions: tcpwm.line_compl[3], scb[0].uart_rts, tcpwm.tr_in[3], scb[0].spi_select0. |+| 33 | EP | passive | Exposed thermal pad, 3.5 x 3.5 mm sawn E-Pad on the package underside. Recommended to solder to a large ground copper pour and tie to VSS for thermal and electrical grounding. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Infineon Cypress Semicon |+| Package | QFN-32(5x5) |+| Category | Embedded Processors & Controllers |+| Pins | 33 |++## Ordering variants++Same part, different packaging or reel option.++- `CY8C4024LQI-S402T`+- `CY8C4024LQI-S412`+- `CY8C4024LQI-S401`+- `CY8C4024LQI-S411`+- `CY8C4024LQI-S403`+- `CY8C4024AXI-S402`+- `CY8C4024AXI-S412`+- `CY8C4024AZI-S403`+- `CY8C4024FNI-S402`+- `CY8C4024FNI-S412`++## CAD (KiCad official)++- Symbol: `CY8C4024LQI-S402T`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: QFN-32(5x5) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Infineon Cypress Semicon datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590221306445791232) (None pp, sha256 `601c482081f165b8`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cy8c4024lqi-s402t-datasheet.pdf)